From fea0019aa86751a4533d7b214866751a9a6e93f1 Mon Sep 17 00:00:00 2001 From: Dennis Date: Wed, 15 Sep 2021 23:42:52 -0700 Subject: [PATCH] Replace old 'reg_clk' name by more generic 'clk' The reason is that the template will always assume that the bus signals and the registers are synchronous. Designers should implement possible synchronization logic outside of this block. --- srdl2sv/components/templates/addrmap.yaml | 3 +-- srdl2sv/components/templates/fields.yaml | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/srdl2sv/components/templates/addrmap.yaml b/srdl2sv/components/templates/addrmap.yaml index 1098a47..dd13524 100644 --- a/srdl2sv/components/templates/addrmap.yaml +++ b/srdl2sv/components/templates/addrmap.yaml @@ -67,8 +67,7 @@ module_declaration: <> ( <> - // Clock & Resets - input reg_clk, + // Resets {resets} // Inputs diff --git a/srdl2sv/components/templates/fields.yaml b/srdl2sv/components/templates/fields.yaml index 6d98113..8cfce55 100644 --- a/srdl2sv/components/templates/fields.yaml +++ b/srdl2sv/components/templates/fields.yaml @@ -1,10 +1,10 @@ --- sense_list_rst: rtl: |- - always_ff @(posedge reg_clk or {rst_edge} {rst_name}) + always_ff @(posedge clk or {rst_edge} {rst_name}) sense_list_no_rst: rtl: |- - always_ff @(posedge reg_clk) + always_ff @(posedge clk) rst_field_assign: rtl: |- if ({rst_negl}{rst_name})