3 Commits

Author	SHA1	Message	Date
Dennis	6719d21423	Fix simple_rw_reg.rdl so that the test passes ... The register was defined as a 64-bit register but the test was written under the assumption it's a 32-bit register. Furthermore, the hardware write-enable flag had to be set since all values would otherwise be overwritten immediately.	2021-10-24 15:43:44 -07:00
Dennis	d3bfdeb3f0	Buswidth is now variable, based on widest register ... Fixes #2.	2021-09-26 21:16:49 -07:00
Dennis	61cd1fbfe3	Add directory that will contain SystemRDL files for tests	2021-09-13 22:09:04 -07:00