57 lines
1.4 KiB
Plaintext
57 lines
1.4 KiB
Plaintext
addrmap enums {
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desc =
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"This example demonstrates how enumerations are translated to Systemverilog, how enumerations are handled when the same enumeration is redefined in different scopes, and hence how enumerations can be re-used in the RTL that surrounds the register block.
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It is not mandatory to use enums in RTL when defining enums in SystemRDL. By providing the command-line argument `--no-enums` all I/O will be defined as flat wires.";
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enum first_enum {
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val_1 = 2'b10;
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val_2 = 2'b01;
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};
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enum second_enum {
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val_3 = 2'b10;
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val_4 = 2'b01;
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};
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reg {
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field {sw=rw; hw=rw;} f1 [1:0];
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field {sw=rw; hw=rw;} f2 [9:8];
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f1->encode = first_enum;
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} reg_a;
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reg {
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field {sw=rw; hw=rw;} f1 [1:0];
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field {sw=rw; hw=rw;} f2 [9:8];
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f1->encode = second_enum;
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} reg_b;
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enum third_enum {
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val_5 = 2'b10;
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val_6 = 2'b01;
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};
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regfile {
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enum fourth_enum {
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val_7 = 2'b10;
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val_8 = 2'b01;
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};
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reg {
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field {sw=rw; hw=rw;} f1 [1:0];
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field {sw=rw; hw=rw;} f2 [9:8];
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f1->encode = third_enum;
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} reg_c;
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reg {
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field {sw=rw; hw=rw;} f1 [1:0];
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field {sw=rw; hw=rw;} f2 [9:8];
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f1->encode = fourth_enum;
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} reg_d;
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} regfile_1;
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};
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