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https://github.com/Silicon1602/srdl2sv.git
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The software is now able to create most interrupt combinations of Section 9.9 of the SystemRDL 2.0 LRM. It supports stickybit/non-stickybit interrupts, it support posedge, negedge, bothedge, and level interrupts, and it is able to generate all surrounding logic. This commit also fixes a reset-bug that caused registers that were reset to 0 to be not reset (because 'if not reset_value' will return True if the 'reset_value' is 0).
57 lines
1.6 KiB
Plaintext
57 lines
1.6 KiB
Plaintext
addrmap interrupts {
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signal { activelow; async; field_reset;} field_reset_n;
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reg {
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field {sw=rw; hw=rw; intr; } intr1 [0:0] = 0;
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field {sw=rw; hw=rw; bothedge intr; } intr2 [1:1] = 0;
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field {sw=rw; hw=rw; negedge intr; } intr3 [2:2] = 0;
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field {sw=rw; hw=rw; posedge intr; } intr4 [3:3] = 0;
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field {sw=rw; hw=rw; } intr5 [4:4] = 0;
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field {sw=rw; hw=rw; nonsticky intr;} intr6 [5:5] = 0;
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} itrs_reg;
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reg {
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field {sw=rw; hw=r;} intr1 [0:0];
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field {sw=rw; hw=r;} intr2 [1:1];
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} itrs_mask;
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reg {
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field {sw=rw; hw=r;} intr5 [1:1];
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} itrs_enable;
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reg {
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field {sw=rw; hw=r;} intr6 [1:1];
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} itrs_next_assign;
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itrs_reg.intr1->mask = itrs_mask.intr1;
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itrs_reg.intr2->mask = itrs_mask.intr2;
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itrs_reg.intr5->enable = itrs_enable.intr5;
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itrs_reg.intr5->next = itrs_next_assign.intr6;
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// HALT REGISTERS
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reg {
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field {sw=rw; hw=rw; intr;} intr1 [0:0];
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field {sw=rw; hw=rw; intr;} intr2 [1:1];
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field {sw=rw; hw=rw; intr;} intr3 [2:2];
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field {sw=rw; hw=rw; } intr4 [3:3];
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field {sw=rw; hw=rw; intr;} intr5 [4:4];
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} itrs_halteable_reg;
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reg {
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field {sw=rw; hw=r;} intr1 [0:0];
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field {sw=rw; hw=r;} intr2 [1:1];
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} itrs_halt;
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itrs_halteable_reg.intr1->haltmask = itrs_halt.intr1;
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itrs_halteable_reg.intr2->haltmask = itrs_halt.intr2;
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// USE INTERRUPT
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reg {
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field {sw=rw; hw=rw;} itrs_reg_next [0:0];
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field {sw=rw; hw=rw;} itrs_halteable_next [1:1];
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} itrs_next;
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itrs_next.itrs_reg_next->next = itrs_reg->intr;
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};
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