104 lines
3.0 KiB
Python
104 lines
3.0 KiB
Python
from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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import cocotb
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import random
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from libs import AMBA3AHBLiteDriver
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@cocotb.test()
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async def test_rclr_rset(dut):
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"""After reset, all rset fields are set to 0 and
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all rclr fields to 255. At the first read, these
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values shall be returned. At the second read, the
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inverse values shall be returned
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"""
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clock = Clock(dut.clk, 1, units="ns") # Create a 10us period clock on port clk
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cocotb.fork(clock.start()) # Start the clock
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bus = AMBA3AHBLiteDriver.AMBA3AHBLiteDriver(dut=dut, nbytes=4)
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# Reset DUT
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dut.field_reset_n <= 0
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await bus.reset()
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dut.field_reset_n <= 1
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await RisingEdge(dut.clk)
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read_return = await bus.read(
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address=0,
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nbytes=4,
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step_size=1)
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assert read_return == {0: 255, 1: 255, 2: 0, 3: 0}, "Reset values of registers are wrong!"
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# After the first read, values should be cleared/set
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read_return = await bus.read(
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address=0,
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nbytes=4,
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step_size=1)
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assert read_return == {0: 0, 1: 0, 2: 255, 3: 255}, "rset/rclr not working propertyl!"
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@cocotb.coroutine
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async def set_wr_enable_1clk_in (clk, hw_wr_enable):
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await RisingEdge(clk)
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hw_wr_enable <= 1
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await RisingEdge(clk)
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hw_wr_enable <= 0
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@cocotb.test()
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async def test_rclr_rset_hw_precedence(dut):
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"""This test is identical to test_rclr_rset
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except that some fields have precendence=hw
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set. In those cases, the fields shall not be
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cleared/set by SW.
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"""
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clock = Clock(dut.clk, 1, units="ns") # Create a 10us period clock on port clk
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cocotb.fork(clock.start()) # Start the clock
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bus = AMBA3AHBLiteDriver.AMBA3AHBLiteDriver(dut=dut, nbytes=4)
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# Reset DUT
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dut.field_reset_n <= 0
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await bus.reset()
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dut.field_reset_n <= 1
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await RisingEdge(dut.clk)
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rand_val = random.randint(0, (1 << 8)-4)
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hw_wr_enable = \
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[dut.read_props_reg__rclr_test_field_hw_wr,
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dut.read_props_reg__rclr_test_field_hw_prec_hw_wr,
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dut.read_props_reg__rset_test_field_hw_wr,
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dut.read_props_reg__rset_test_field_hw_prec_hw_wr]
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dut.read_props_reg__rclr_test_field_in <= rand_val
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dut.read_props_reg__rclr_test_field_hw_prec_in <= rand_val + 1
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dut.read_props_reg__rset_test_field_in <= rand_val + 2
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dut.read_props_reg__rset_test_field_hw_prec_in <= rand_val + 3
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for i in range (0, 4):
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cocotb.fork(set_wr_enable_1clk_in(dut.clk, hw_wr_enable[i]))
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read_return = await bus.read(
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address=i,
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nbytes=1,
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step_size=1)
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dut._log.info(f"Read {read_return}.")
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assert read_return == {i: 255 if i < 2 else 0}, f"Read out value of address {i} incorrect"
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# After the first read, values should be cleared/set
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read_return = await bus.read(
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address=0,
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nbytes=4,
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step_size=1)
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dut._log.info("Read {read_return}.")
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assert read_return == {0: 0, 1: rand_val + 1, 2: 255, 3: rand_val + 3}, "precendence not working as intended!"
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