mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-09-21 08:40:25 +00:00
Dennis
24d5534037
Every single field and every single alias (!) has its own interface to the surrounding hardware. This is required to give users the maximum amount of freedom when defining certain properties in RDL.
47 lines
1.1 KiB
Plaintext
47 lines
1.1 KiB
Plaintext
addrmap external_registers {
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reg {
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field {} f1 [15:0];
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field {} f2 [31:16];
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f2->sw = w;
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} reg_int0;
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// The registers below shall not be implemented by RTL that is
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// generated by srdl2sv but rather, the tool shall provide an
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// interface to communicate with the bus.
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external reg {
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field {} f1 [15:0];
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field {} f2 [31:16];
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f2->sw = w;
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} reg_ext0;
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// Multi-dimensional registers must work
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external reg {
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field {} f1 [15:0];
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field {} f2 [31:20];
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f2->sw = w;
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} reg_ext1 [2];
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external reg {
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field {} f1 [14:3];
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field {} f2 [31:20];
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f1->sw = rw;
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f2->sw = rw;
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} reg_ext2 [2];
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// Add an alias to verify that alias capabilities work fine for
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// external registers
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reg reg_ext2_alias_t {
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field {} f1 [14:3];
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f1->sw = rw;
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};
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external alias reg_ext2 reg_ext2_alias_t reg_ext2_alias;
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reg {
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field {} f1 [15:0];
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field {} f2 [31:16];
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f2->sw = w;
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} reg_int1 [2];
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};
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