100 lines
7.7 KiB
Plaintext
100 lines
7.7 KiB
Plaintext
verilator -cc -sv srdl2sv_out/aliases.sv srdl2sv_out/srdl2sv_amba3ahblite.sv srdl2sv_out/srdl2sv_widget_if.sv
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%Error: srdl2sv_out/aliases.sv:103:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_w_ack'
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103 | input example_rf__ext_main_reg__f1_ext_w_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:98:25: ... Location of original declaration
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98 | input example_rf__ext_main_reg__f1_ext_w_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:104:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_w_err'
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104 | input example_rf__ext_main_reg__f1_ext_w_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:97:25: ... Location of original declaration
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97 | input example_rf__ext_main_reg__f1_ext_w_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:109:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_r_ack'
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109 | input example_rf__ext_main_reg__f1_ext_r_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:94:25: ... Location of original declaration
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94 | input example_rf__ext_main_reg__f1_ext_r_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:110:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_r_err'
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110 | input example_rf__ext_main_reg__f1_ext_r_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:93:25: ... Location of original declaration
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93 | input example_rf__ext_main_reg__f1_ext_r_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:118:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_w_ack'
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118 | input example_rf__ext_main_reg__f2_ext_w_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:100:25: ... Location of original declaration
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100 | input example_rf__ext_main_reg__f2_ext_w_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:119:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_w_err'
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119 | input example_rf__ext_main_reg__f2_ext_w_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:99:25: ... Location of original declaration
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99 | input example_rf__ext_main_reg__f2_ext_w_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:124:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_r_ack'
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124 | input example_rf__ext_main_reg__f2_ext_r_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:96:25: ... Location of original declaration
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96 | input example_rf__ext_main_reg__f2_ext_r_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:125:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_r_err'
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125 | input example_rf__ext_main_reg__f2_ext_r_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:95:25: ... Location of original declaration
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95 | input example_rf__ext_main_reg__f2_ext_r_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:103:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_w_ack'
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103 | input example_rf__ext_main_reg__f1_ext_w_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:98:25: ... Location of original declaration
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98 | input example_rf__ext_main_reg__f1_ext_w_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:104:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_w_err'
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104 | input example_rf__ext_main_reg__f1_ext_w_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:97:25: ... Location of original declaration
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97 | input example_rf__ext_main_reg__f1_ext_w_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:109:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_r_ack'
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109 | input example_rf__ext_main_reg__f1_ext_r_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:94:25: ... Location of original declaration
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94 | input example_rf__ext_main_reg__f1_ext_r_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:110:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_r_err'
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110 | input example_rf__ext_main_reg__f1_ext_r_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:93:25: ... Location of original declaration
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93 | input example_rf__ext_main_reg__f1_ext_r_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:118:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_w_ack'
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118 | input example_rf__ext_main_reg__f2_ext_w_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:100:25: ... Location of original declaration
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100 | input example_rf__ext_main_reg__f2_ext_w_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:119:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_w_err'
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119 | input example_rf__ext_main_reg__f2_ext_w_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:99:25: ... Location of original declaration
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99 | input example_rf__ext_main_reg__f2_ext_w_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:124:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_r_ack'
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124 | input example_rf__ext_main_reg__f2_ext_r_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:96:25: ... Location of original declaration
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96 | input example_rf__ext_main_reg__f2_ext_r_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:125:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_r_err'
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125 | input example_rf__ext_main_reg__f2_ext_r_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:95:25: ... Location of original declaration
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95 | input example_rf__ext_main_reg__f2_ext_r_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: Exiting due to 16 error(s)
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make: *** [Makefile:8: verilog_compile] Error 1
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