312 lines
9.4 KiB
Systemverilog
312 lines
9.4 KiB
Systemverilog
/*
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* Copyright 2021 Dennis Potter <dennis@dennispotter.eu>
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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module srdl2sv_amba3ahblite #(
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parameter bit FLOP_REGISTER_IF = 0,
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parameter BUS_BITS = 32,
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parameter NO_BYTE_ENABLE = 0
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)
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(
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// Bus protocol
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input HCLK,
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input HRESETn,
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input HSEL,
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input [31:0] HADDR,
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input HWRITE,
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input [ 2:0] HSIZE,
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input [ 3:0] HPROT, // Might be used in the future together with an RDL UDP
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input [ 1:0] HTRANS,
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input [BUS_BITS-1:0] HWDATA,
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output logic HREADYOUT,
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output logic HRESP,
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output logic [BUS_BITS-1:0] HRDATA,
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// Interface to internal logic
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srdl2sv_widget_if.widget widget_if
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);
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localparam BUS_BYTES = BUS_BITS/8;
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localparam BUS_BYTES_W = $clog2(BUS_BYTES);
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/***********************
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* Define enums
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***********************/
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typedef enum logic [2:0] {
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SINGLE = 3'b000,
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INCR = 3'b001,
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WRAP4 = 3'b010,
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INCR4 = 3'b011,
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WRAP8 = 3'b100,
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INCR8 = 3'b101,
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WRAP16 = 3'b110,
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INCR16 = 3'b111
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} HBURST_t;
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typedef enum logic [1:0] {
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IDLE = 2'b00,
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BUSY = 2'b01,
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NONSEQ = 2'b10,
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SEQ = 2'b11
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} HTRANS_t;
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typedef enum logic {
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OKAY = 1'b0,
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ERROR = 1'b1
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} HRESP_t;
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typedef enum logic {
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READ = 1'b0,
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WRITE = 1'b1
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} OP_t;
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typedef enum logic [1:0] {
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FSM_IDLE = 2'b00,
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FSM_TRANS = 2'b01,
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FSM_ERR_0 = 2'b10,
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FSM_ERR_1 = 2'b11
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} fsm_t;
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/****************************
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* Determine current address
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****************************/
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logic [31:0] HADDR_q;
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logic [2:0] HSIZE_q;
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OP_t operation_q;
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wire addr_err = HADDR % (32'b1 << HSIZE) != 32'b0;
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always_ff @ (posedge HCLK)
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begin
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case (HTRANS)
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IDLE: ;// Do nothing
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BUSY: ;// Do nothing
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NONSEQ:
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begin
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// When a transfer is extended it has the side-effecxt
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// of extending the address phase of the next transfer
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if (HREADYOUT)
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begin
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HADDR_q <= HADDR;
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HSIZE_q <= HSIZE;
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operation_q <= HWRITE ? WRITE : READ;
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end
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end
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SEQ:
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begin
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if (HREADYOUT)
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begin
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HADDR_q <= HADDR;
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HSIZE_q <= HSIZE;
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end
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end
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endcase
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end
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/****************************
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* Statemachine
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****************************/
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logic [BUS_BITS-1:0] HRDATA_temp;
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fsm_t fsm_next, fsm_q;
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always_comb
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begin
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// Defaults
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HREADYOUT = 1'b1;
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HRESP = OKAY;
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// When reading back, the data of the bit that was accessed over the bus
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// should be at byte 0 of the HRDATA bus and bits that were not accessed
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// should be masked with 0s.
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HRDATA_temp = widget_if.r_data >> (8*HADDR_q[BUS_BYTES_W-1:0]);
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for (int i = 0; i < BUS_BYTES; i++)
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if (i < (1 << HSIZE_q))
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HRDATA[8*(i+1)-1 -: 8] = HRDATA_temp[8*(i+1)-1 -: 8];
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else
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HRDATA[8*(i+1)-1 -: 8] = 8'b0;
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widget_if_w_vld_next = 0;
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widget_if_r_vld_next = 0;
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fsm_next = fsm_q;
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case (fsm_q)
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default: // FSM_IDLE
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begin
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if (HSEL && HTRANS > BUSY)
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begin
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if (addr_err)
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// In case the address is illegal, switch to an error state
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fsm_next = FSM_ERR_0;
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else if (HTRANS == NONSEQ)
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// If NONSEQ, go to NONSEQ state
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fsm_next = FSM_TRANS;
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else if (HTRANS == SEQ)
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// If a SEQ is provided, something is wrong
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fsm_next = FSM_ERR_0;
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end
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end
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FSM_TRANS:
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begin
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HREADYOUT = widget_if.rdy;
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widget_if_w_vld_next = operation_q == WRITE;
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widget_if_r_vld_next = operation_q == READ;
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if (HTRANS == BUSY)
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begin
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// Wait
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fsm_next = FSM_TRANS;
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end
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else if (widget_if.err && widget_if.rdy)
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begin
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HREADYOUT = 0;
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HRESP = ERROR;
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fsm_next = FSM_ERR_1;
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end
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else if (HTRANS == NONSEQ)
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begin
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// Another unrelated access is coming
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fsm_next = FSM_TRANS;
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end
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else if (HTRANS == SEQ)
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begin
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// Another part of the burst is coming
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fsm_next = FSM_TRANS;
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end
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else if (HTRANS == IDLE)
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begin
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// All done, wrapping things up!
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fsm_next = widget_if.rdy ? FSM_IDLE : FSM_TRANS;
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end
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end
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FSM_ERR_0:
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begin
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HREADYOUT = 0;
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if (HTRANS == BUSY)
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begin
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// Slaves must always provide a zero wait state OKAY response
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// to BUSY transfers and the transfer must be ignored by the slave.
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HRESP = OKAY;
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fsm_next = FSM_ERR_0;
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end
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else
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begin
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HRESP = ERROR;
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fsm_next = FSM_ERR_1;
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end
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end
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FSM_ERR_1:
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begin
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if (HTRANS == BUSY)
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begin
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// Slaves must always provide a zero wait state OKAY response
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// to BUSY transfers and the transfer must be ignored by the slave.
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HREADYOUT = 0;
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HRESP = OKAY;
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fsm_next = FSM_ERR_0;
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end
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else
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begin
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HREADYOUT = 1;
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HRESP = ERROR;
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fsm_next = FSM_IDLE;
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end
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end
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endcase
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end
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always_ff @ (posedge HCLK or negedge HRESETn)
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if (!HRESETn)
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fsm_q <= FSM_IDLE;
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else
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fsm_q <= fsm_next;
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/***
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* Determine the number of active bytes
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***/
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logic [BUS_BYTES-1:0] HSIZE_bitfielded;
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logic [BUS_BYTES-1:0] widget_if_byte_en_next;
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logic widget_if_w_vld_next;
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logic widget_if_r_vld_next;
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generate
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if (NO_BYTE_ENABLE)
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begin
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assign widget_if_byte_en_next = {BUS_BYTES{1'b1}};
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end
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else
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begin
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always_comb
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begin
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for (int i = 0; i < BUS_BYTES; i++)
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HSIZE_bitfielded[i] = i < (1 << HSIZE_q);
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// Shift if not the full bus is accessed
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widget_if_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
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end
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end
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endgenerate
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/***
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* Drive interface to registers
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***/
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generate
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if (FLOP_REGISTER_IF)
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begin
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always_ff @ (posedge HCLK or negedge HRESETn)
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if (!HRESETn)
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begin
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widget_if.w_vld <= 1'b0;
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widget_if.r_vld <= 1'b0;
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end
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else
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begin
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widget_if.w_vld <= widget_if_w_vld_next;
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widget_if.r_vld <= widget_if_r_vld_next;
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end
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always_ff @ (posedge HCLK)
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begin
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widget_if.addr <= {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
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widget_if.w_data <= HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
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widget_if.byte_en <= widget_if_byte_en_next;
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end
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end
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else
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begin
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assign widget_if.w_vld = widget_if_w_vld_next;
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assign widget_if.r_vld = widget_if_r_vld_next;
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assign widget_if.addr = {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
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assign widget_if.w_data = HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
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assign widget_if.byte_en = widget_if_byte_en_next;
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end
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endgenerate
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endmodule
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