406 lines
15 KiB
Python
406 lines
15 KiB
Python
import importlib.resources as pkg_resources
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import sys
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import getpass
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import socket
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import time
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import os
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import yaml
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from systemrdl import node
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# Local packages
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from srdl2sv.components.component import Component
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from srdl2sv.components.regfile import RegFile
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from srdl2sv.components.register import Register
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from srdl2sv.components.memory import Memory
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from srdl2sv.components import templates
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from srdl2sv.components import widgets
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class AddrMap(Component):
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# Save YAML template as class variable
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templ_dict = yaml.load(
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pkg_resources.read_text(templates, 'addrmap.yaml'),
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Loader=yaml.FullLoader)
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def __init__(self, obj: node.RootNode, config: dict):
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super().__init__(
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obj=obj,
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config=config,
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parents_strides=None,
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parents_dimensions=None)
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# Check if global resets are defined
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glbl_settings = {}
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# Use global settings to define whether a component is already in a generate block
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glbl_settings['generate_active'] = False
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# Save whether 0, 1, or x must be set for reserved bits
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if self.obj.get_property('rsvdset'):
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glbl_settings['rsvd_val'] = "1"
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elif self.obj.get_property('rsvdsetX'):
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glbl_settings['rsvd_val'] = "x"
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else:
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glbl_settings['rsvd_val'] = "0"
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# Empty dictionary of register objects
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# We need a dictionary since it might be required to access the objects later
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# by name (for example, in case of aliases)
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self.registers = {}
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self.regfiles = {}
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self.mems = {}
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self.regwidth = 0
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# Traverse through children
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for child in self.obj.children():
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if isinstance(child, node.AddrmapNode):
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# This addressmap opens a completely new scope. For example,
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# a field_reset does not propagate through to this scope.
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self.logger.info('Found hierarchical addrmap. Entering it...')
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self.logger.error('Child addrmaps are not implemented yet!')
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elif isinstance(child, node.RegfileNode):
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new_child = RegFile(
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obj=child,
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parents_dimensions=None,
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parents_strides=None,
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config=config,
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glbl_settings=glbl_settings)
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self.regfiles[child.inst_name] = new_child
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elif isinstance(child, node.MemNode):
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new_child = Memory(
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obj=child,
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parents_dimensions=None,
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parents_strides=None,
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config=config,
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glbl_settings=glbl_settings)
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new_child.sanity_checks()
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self.mems[child.inst_name] = new_child
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elif isinstance(child, node.RegNode):
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if child.inst.is_alias:
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# If the node we found is an alias, we shall not create a
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# new register. Rather, we bury up the old register and add
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# additional properties
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self.registers[child.inst.alias_primary_inst.inst_name]\
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.add_alias(child)
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else:
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new_child = Register(
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obj=child,
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parents_dimensions=None,
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parents_strides=None,
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config=config,
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glbl_settings=glbl_settings)
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self.registers[child.inst_name] = new_child
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try:
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if (regwidth := new_child.get_regwidth()) > self.regwidth:
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self.regwidth = regwidth
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except KeyError:
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# Simply ignore nodes like SignalNodes
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pass
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self.logger.info(
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f"Detected maximum register width of whole addrmap to be '{self.regwidth}'")
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# Add registers to children. This must be done in a last step
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# to account for all possible alias combinations
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self.children = {**self.regfiles, **self.registers, **self.mems}
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self.logger.info("Done generating all child-regfiles/registers")
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# Create RTL of all registers. Registers in regfiles are
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# already built and so are memories.
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for register in self.registers.values():
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register.create_rtl()
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# Add bus widget ports
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widget_rtl = self.__get_widget_ports_rtl()
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# Start assembling addrmap module
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self.logger.info("Starting to assemble input & output ports")
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# Reset ports
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reset_ports_rtl = [
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AddrMap.templ_dict['reset_port']['rtl'].format(
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name = name)
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for name in self.get_resets()
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]
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# Prefetch dictionaries in local array
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input_dict_list = self.get_ports('input').items()
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output_dict_list = self.get_ports('output').items()
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input_signal_width = min(
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max([len(value[0]) for (_, value) in input_dict_list]), 40)
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input_name_width = min(
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max([len(key) for (key, _) in input_dict_list]), 40)
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output_signal_width = min(
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max([len(value[0]) for (_, value) in output_dict_list]), 40)
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output_name_width = min(
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max([len(key) for (key, _) in output_dict_list]), 40)
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# Input ports
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# Yay for unreadable code....
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input_ports_rtl = [
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AddrMap.templ_dict['input_port']['rtl'].format(
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name = key,
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signal_type = value[0],
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signal_width = input_signal_width,
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name_width = input_name_width,
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unpacked_dim = '[{}]'.format(
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']['.join(
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[str(y) for y in value[1]]))
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if value[1] else '')
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for (key, value) in input_dict_list
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]
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# Output ports
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output_ports_rtl = [
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AddrMap.templ_dict['output_port']['rtl'].format(
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name = key,
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signal_width = output_signal_width,
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name_width = output_name_width,
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signal_type = value[0],
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unpacked_dim = '[{}]'.format(
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']['.join(
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[str(y) for y in value[1]]))
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if value[1] else '')
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for (key, value) in output_dict_list
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]
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# Remove comma from last port entry
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output_ports_rtl[-1] = output_ports_rtl[-1].rstrip(',')
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# Define packages to be included. Always include the
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# b2w and w2b defines.
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import_package_list = [
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AddrMap.templ_dict['import_package']['rtl'].format(
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name = 'srdl2sv_if'),
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'\n'
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]
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try:
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for pkg_name in self.__get_package_names():
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import_package_list.append(
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AddrMap.templ_dict['import_package']['rtl'].format(name = pkg_name)
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)
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import_package_list.append('\n')
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except IndexError:
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pass
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import_package_list.pop()
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self.rtl_header.append(
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AddrMap.templ_dict['header'].format(
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user = getpass.getuser(),
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time = time.strftime('%B %d %Y %H:%M:%S', config['ts']),
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year = time.strftime('%Y', config['ts']),
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version = config['version'],
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path = os.getcwd(),
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rdl_file = config['input_file'],
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incdirs = '\n * - '.join(config['search_paths']),
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config = '\n * - '.join(config['list_args']),
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addrmap = self.name.upper(),
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host = socket.gethostname()))
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self.rtl_header.append(
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AddrMap.templ_dict['module_declaration']['rtl'].format(
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name = self.name,
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import_package_list = ''.join(import_package_list),
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resets = '\n'.join(reset_ports_rtl),
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inputs = '\n'.join(input_ports_rtl),
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outputs = '\n'.join(output_ports_rtl)))
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# Add description, if applicable
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self.rtl_header.append(self.get_description())
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# Add wire/register instantiations
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self.__add_signal_instantiation()
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# Add bus widget RTL
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self.rtl_header.append(widget_rtl)
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# Append genvars
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self.__append_genvars()
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# Create read multiplexer
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self.__create_mux_string()
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# Add endmodule keyword
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self.rtl_footer.append('endmodule')
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def __create_mux_string(self):
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list_of_cases = []
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# Add an entry for each version of a register
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for child in self.children.values():
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for mux_entry_dim in child.create_mux_string():
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# Data structure of mux_entry:
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r2b_data = ''.join([mux_entry_dim.mux_entry.data_wire, mux_entry_dim.dim])
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r2b_rdy = ''.join([mux_entry_dim.mux_entry.rdy_wire, mux_entry_dim.dim])
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r2b_err = ''.join([mux_entry_dim.mux_entry.err_wire, mux_entry_dim.dim])
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active_wire = ''.join([mux_entry_dim.mux_entry.active_wire, mux_entry_dim.dim])
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list_of_cases.append(
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AddrMap.templ_dict['list_of_mux_cases']['rtl'].format(
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active_wire = active_wire,
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r2b_data = r2b_data,
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r2b_rdy = r2b_rdy,
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r2b_err = r2b_err)
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)
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# Define default case
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list_of_cases.append(AddrMap.templ_dict['default_mux_case']['rtl'])
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self.rtl_footer.append(
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self._process_yaml(
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AddrMap.templ_dict['read_mux'],
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{'list_of_cases': '\n'.join(list_of_cases)}
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)
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)
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def __add_signal_instantiation(self):
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dict_list = list(self.get_signals(True).items())
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signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)
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name_width = min(max([len(key) for (key, _) in dict_list]), 40)
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self.rtl_header = [
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*self.rtl_header,
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'',
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'// Internal signals',
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*[AddrMap.templ_dict['signal_declaration'].format(
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name = key,
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type = value[0],
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signal_width = signal_width,
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name_width = name_width,
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unpacked_dim = '[{}]'.format(
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']['.join(
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[str(y) for y in value[1]]))
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if value[1] else '')
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for (key, value) in dict_list],
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''
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]
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def __get_widget_ports_rtl(self):
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self.widget_templ_dict = yaml.load(
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pkg_resources.read_text(widgets, f"srdl2sv_{self.config['bus']}.yaml"),
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Loader=yaml.FullLoader)
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return self._process_yaml(
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self.widget_templ_dict['module_instantiation'],
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{'bus_width': self.regwidth,
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'no_byte_enable': 1 if self.config['no_byte_enable'] else 0,
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}
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)
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def __append_genvars(self):
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genvars = ', '.join([''.join(['gv_', chr(97+i)])
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for i in range(self.get_max_dim_depth())])
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if genvars:
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genvars_instantiation = ''.join([
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'\ngenvar ',
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genvars,
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';\n'
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])
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self.rtl_header.append(genvars_instantiation)
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def __get_package_names(self) -> set():
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names = set()
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for register in self.registers.values():
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for typedef in register.get_typedefs().values():
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names.add(typedef.scope)
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for regfile in self.regfiles.values():
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names.update(regfile.get_package_names())
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return names
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def get_package_rtl(self, tab_width: int = 4, real_tabs = False) -> dict():
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if not self.config['enums']:
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return {}
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# First go through all registers in this scope to generate a package
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package_rtl = []
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rtl_return = {}
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# Need to keep track of enum names since they shall be unique
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# per scope
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enum_rtl = {}
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enum_rtl[self.name] = []
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enum_members = {}
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for i in self.registers.values():
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for key, value in i.get_typedefs().items():
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variable_list = []
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max_name_width = min(
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max([len(x[0]) for x in value.members]), 40)
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for var in value.members:
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if var[0] not in enum_members:
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enum_members[var[0]] = "::".join([self.name, key])
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else:
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self.logger.fatal(
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f"Enum member '{var[0]}' was found at multiple locations in the same "\
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"main scope: \n"\
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f" -- 1st occurance: '{enum_members[var[0]]}'\n"\
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f" -- 2nd occurance: '{'::'.join([self.name, key])}'\n\n"\
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"This is not legal because all these enums will be defined "\
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"in the same SystemVerilog scope. To share the same enum among "\
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"different registers, define them on a higher level in the "\
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"hierarchy.\n\n"\
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"Exiting...")
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sys.exit(1)
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variable_list.append(
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AddrMap.templ_dict['enum_var_list_item']['rtl'].format(
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value = var[1],
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width = value.width,
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max_name_width = max_name_width,
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name = var[0]))
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enum_rtl[self.name].append(
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AddrMap.templ_dict['enum_declaration']['rtl'].format(
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width=value.width-1,
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name = key,
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enum_var_list = ',\n'.join(variable_list)))
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# Invoke get_package_rtl method from regfiles
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for regfile in self.regfiles.values():
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for key, value in regfile.get_package_rtl().items():
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if key in enum_rtl:
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enum_rtl[key] = [*enum_rtl[key], *value]
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else:
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enum_rtl[key] = value
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# Create RTL to return
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for key, value in enum_rtl.items():
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if not value:
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# Skip if package wouldn't contain any enums
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continue
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package_rtl =\
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AddrMap.templ_dict['package_declaration']['rtl'].format(
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name = key,
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pkg_content = '\n\n'.join(value))
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rtl_return[key] = AddrMap.add_tabs(
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package_rtl,
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tab_width,
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real_tabs)
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return rtl_return
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