395 lines
13 KiB
Python
395 lines
13 KiB
Python
import re
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import math
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import sys
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from typing import NamedTuple, Optional
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from dataclasses import dataclass
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from systemrdl import node
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# Local modules
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from srdl2sv.log.log import create_logger
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# Define NamedTuple
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class TypeDef(NamedTuple):
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scope: str
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width: int
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members: tuple
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@dataclass
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class SWMuxEntry:
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data_wire: str
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rdy_wire: str
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err_wire: str
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active_wire: str
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@dataclass
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class SWMuxEntryDimensioned():
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mux_entry: SWMuxEntry
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dim: str
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class Component():
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def __init__(
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self,
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obj,
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config,
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parents_dimensions: Optional[list] = None,
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parents_strides: Optional[list] = None):
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self.rtl_header = []
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self.rtl_footer = []
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self.children = {}
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self.typedefs = {}
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self.ports = {}
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self.resets = set()
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self.signals = {}
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self.ports['input'] = {}
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self.ports['output'] = {}
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self.field_type = ''
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# Save object
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# TODO: should probably be list because of alias registers
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self.obj = obj
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# Save name
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self.name = obj.inst_name
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# Create path
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self.create_underscored_path()
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# Save config
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self.config = config.copy()
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# Generate all variables that have anything to do with dimensions or strides
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self.__init_dimensions(parents_dimensions)
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self.__init_strides(parents_strides)
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# Save and/or process important variables
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self.__init_variables()
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# Create logger object
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self.__create_logger(self.full_path, config)
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self.logger.debug(f"Starting to process {self.__class__.__name__} '{obj.inst_name}'")
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def __init_variables(self):
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# By default, registers and fields are not interrupt registers
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self.properties = {
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'intr': False,
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'halt': False,
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'swmod': False,
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'swacc': False,
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'sw_rd': False,
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'sw_wr': False,
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'sw_rd_wire': False,
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'sw_wr_wire': False,
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}
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self.genvars_str = ''
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def __create_logger(self, name: str, config: dict):
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self.logger = create_logger(
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name,
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stream_log_level=config['stream_log_level'],
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file_log_level=config['file_log_level'],
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file_name=config['file_log_location'])
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self.logger.propagate = False
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def __init_dimensions(self, parents_dimensions):
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# Determine dimensions of register
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self.sel_arr = 'single'
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self.total_array_dimensions = parents_dimensions if parents_dimensions else []
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self.own_array_dimensions = []
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try:
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if self.obj.is_array:
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self.sel_arr = 'array'
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self.total_array_dimensions = [*self.total_array_dimensions,
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*self.obj.array_dimensions]
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self.own_array_dimensions = self.obj.array_dimensions
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except AttributeError:
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pass
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# How many dimensions were already part of some higher up hierarchy?
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self.parents_depths = len(parents_dimensions) if parents_dimensions else 0
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# Calculate depth and number of dimensions
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self.own_depth = '[{}]'.format(']['.join(f"{i}" for i in self.own_array_dimensions))
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self.own_dimensions = len(self.own_array_dimensions)
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self.total_dimensions = len(self.total_array_dimensions)
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def __init_strides(self, parents_strides):
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self.total_stride = parents_strides if parents_strides else []
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try:
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if self.obj.is_array:
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# Merge parent's stride with stride of this regfile. Before doing so, the
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# respective stride of the different dimensions shall be calculated
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self.total_stride = [
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*self.total_stride,
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*[math.prod(self.own_array_dimensions[i+1:])
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*self.obj.array_stride
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for i, _ in enumerate(self.own_array_dimensions)]
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]
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except AttributeError:
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# Not all Nodes can be an array. In that case, just take the parent's stride
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pass
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def _init_genvars(self):
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# Calculate how many genvars shall be added
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genvars = [f"[gv_{chr(97+i)}]" for i in range(self.total_dimensions)]
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self.genvars_str = ''.join(genvars)
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def get_resets(self):
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self.logger.debug("Return reset list")
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for child in self.children.values():
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self.resets |= child.get_resets()
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return self.resets
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def get_ports(self, port_type: str):
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self.logger.debug("Return port list")
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for child in self.children.values():
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self.ports[port_type] |= child.get_ports(port_type)
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return self.ports[port_type]
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def get_max_dim_depth(self) -> int:
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self.logger.debug(f"Return depth '{self.total_dimensions}' for dimensions (including "\
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f"parents) '{self.total_array_dimensions}'")
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return max([
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self.total_dimensions,
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*[x.get_max_dim_depth() for x in self.children.values()]
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])
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def get_signals(self, no_children = False):
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self.logger.debug("Return signal list")
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if not no_children:
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for child in self.children.values():
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self.signals |= child.get_signals()
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return self.signals
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def get_typedefs(self):
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self.logger.debug("Return typedef list")
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for child in self.children.values():
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self.typedefs |= child.get_typedefs()
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return self.typedefs
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def get_rtl(self, tab_width: int = 0, real_tabs: bool = False) -> str:
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self.logger.debug("Return RTL")
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# Loop through children and append RTL
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rtl_children = []
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for child in self.children.values():
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rtl_children.append(child.get_rtl())
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# Concatenate header, main, and footer
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rtl = [*self.rtl_header, *rtl_children, *self.rtl_footer]
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# Join lists and return string
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if tab_width > 0:
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return Component.add_tabs(
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'\n'.join(rtl),
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tab_width,
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real_tabs)
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return '\n'.join(rtl)
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@staticmethod
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def add_tabs(rtl: str, tab_width: int = 4, real_tabs = False) -> str:
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indent_lvl = 0
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indent_lvl_next = 0
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# Define tab style
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tab = "\t" if real_tabs else " "
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tab = tab_width * tab
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# Define triggers for which the indentation level will increment or
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# decrement on the next line
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trigger_re = re.compile(r"""
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.*?(?P<keyword>
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(?:\bbegin\b|\{|\bcase\b|<<INDENT>>)|
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(?:\bend\b|}|\bendcase\b|<<UNINDENT>>)
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)(?P<remainder>[^$]*)
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""", flags=re.VERBOSE)
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rtl_indented = []
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# Go through RTL, line by line
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for line in rtl.split('\n', -1):
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line_split = line
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# This is done because the increment of the indent level must
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# be delayed one cycle
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indent_lvl = indent_lvl_next
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while 1:
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# Check if indentation must be decremented
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if match_obj := trigger_re.match(line_split):
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if match_obj.group('keyword') in ('begin', '{', 'case', '<<INDENT>>'):
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indent_lvl_next += 1
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else:
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indent_lvl = indent_lvl_next - 1
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indent_lvl_next -= 1
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line_split = match_obj.group('remainder')
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if not line_split:
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break
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else:
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break
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# Add tabs
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if line.strip() not in ("<<INDENT>>", "<<UNINDENT>>", "<<SQUASH_NEWLINE>>"):
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rtl_indented.append(f"{tab*indent_lvl}{line}")
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return '\n'.join(rtl_indented)
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@staticmethod
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def __get_underscored_path(path: str, owning_addrmap: str):
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return path\
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.replace('[]', '')\
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.replace(f"{owning_addrmap}.", '')\
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.replace('.', '__')
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@staticmethod
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def __split_dimensions(path: str):
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re_dimensions = re.compile(r'(\[[^]]*\])')
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new_path = re_dimensions.sub('', path)
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return (new_path, ''.join(re_dimensions.findall(path)))
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def get_signal_name(self, obj):
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name = []
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try:
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child_obj = obj.node
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except AttributeError:
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child_obj = obj
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split_name = self.__split_dimensions(
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self.__get_underscored_path(
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child_obj.get_path(),
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child_obj.owning_addrmap.inst_name)
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)
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name.append(split_name[0])
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if isinstance(obj, node.FieldNode):
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name.append('_q')
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elif isinstance(obj, node.SignalNode):
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# Must add it to signal list
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self.ports['input'][obj.inst_name] =\
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("logic" if obj.width == 1 else f"logic [{obj.width}:0]", [])
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else:
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name.append('_')
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name.append(obj.name)
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# This is a property. Check if the original field actually has this property
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if obj.name in ("intr", "halt"):
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pass
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elif not obj.node.get_property(obj.name):
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self.logger.fatal(f"Reference to the property '{obj.name}' of instance "
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f"'{obj.node.get_path()}' found. This instance does "
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"hold the reference property! Please fix this if you "
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"want me to do my job properly.")
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sys.exit(1)
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name.append(split_name[1])
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return ''.join(name)
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def _process_yaml(self,
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yaml_obj,
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values: dict = {},
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skip_signals: bool = False,
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skip_inputs: bool = False,
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skip_outputs: bool = False):
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try:
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if skip_signals:
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raise KeyError
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for signal in yaml_obj['signals']:
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try:
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array_dimensions = [] if signal['no_unpacked'] \
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else self.total_array_dimensions
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except KeyError:
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array_dimensions = self.total_array_dimensions
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self.signals[signal['name'].format(**values)] =\
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(signal['signal_type'].format(**values),
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array_dimensions)
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except (TypeError, KeyError):
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pass
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try:
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if skip_inputs:
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raise KeyError
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for input_p in yaml_obj['input_ports']:
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try:
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array_dimensions = [] if input_p['no_unpacked'] \
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else self.total_array_dimensions
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except KeyError:
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array_dimensions = self.total_array_dimensions
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self.ports['input'][input_p['name'].format(**values)] =\
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(input_p['signal_type'].format(**values),
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array_dimensions)
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except (TypeError, KeyError):
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pass
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try:
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if skip_outputs:
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raise KeyError
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for output_p in yaml_obj['output_ports']:
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try:
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array_dimensions = [] if output_p['no_unpacked'] \
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else self.total_array_dimensions
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except KeyError:
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array_dimensions = self.total_array_dimensions
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self.ports['output'][output_p['name'].format(**values)] =\
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(output_p['signal_type'].format(**values),
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array_dimensions)
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except (TypeError, KeyError):
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pass
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# Return RTL with values
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return yaml_obj['rtl'].format(**values)
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def create_underscored_path(self):
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self.owning_addrmap, self.full_path, self.path, self.path_underscored =\
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Component.create_underscored_path_static(self.obj)
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@staticmethod
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def create_underscored_path_static(obj):
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owning_addrmap = obj.owning_addrmap.inst_name
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full_path = Component.__split_dimensions(obj.get_path())[0]
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path = full_path.replace(f"{owning_addrmap}.", '')
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path_underscored = path.replace('.', '__')
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return (owning_addrmap, full_path, path, path_underscored)
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def get_description(self):
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if self.config['descriptions'][self.__class__.__name__]:
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if desc := self.obj.get_property('desc'):
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return self.process_yaml(
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self.templ_dict['description'],
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{'desc': desc},
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)
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return ''
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def get_regwidth(self) -> int:
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return self.regwidth
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