228 lines
8.5 KiB
Python
228 lines
8.5 KiB
Python
import importlib.resources as pkg_resources
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import sys
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import math
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import yaml
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from typing import Optional
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from systemrdl import node
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from systemrdl.node import FieldNode
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# Local packages
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from srdl2sv.components.component import Component
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from srdl2sv.components.register import Register
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from srdl2sv.components import templates
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class RegFile(Component):
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# Save YAML template as class variable
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templ_dict = yaml.load(
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pkg_resources.read_text(templates, 'regfile.yaml'),
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Loader=yaml.FullLoader)
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def __init__(
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self,
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obj: node.RegfileNode,
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config: dict,
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parents_dimensions: Optional[list],
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parents_strides: Optional[list],
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glbl_settings: dict):
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super().__init__(
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obj=obj,
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config=config,
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parents_strides=parents_strides,
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parents_dimensions=parents_dimensions)
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# Empty dictionary of register objects
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# We need a dictionary since it might be required to access the objects later
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# by name (for example, in case of aliases)
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self.registers = {}
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self.regfiles = {}
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# Set object to 0 for easy addressing
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self.obj.current_idx = [0]
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# Determine whether this regfile must add a generate block and for-loop
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if self.own_dimensions and not glbl_settings['generate_active']:
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self.generate_initiated = True
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glbl_settings['generate_active'] = True
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else:
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self.generate_initiated = False
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self.regwidth = 0
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# Traverse through children
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for child in obj.children():
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if isinstance(child, node.AddrmapNode):
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self.logger.fatal('Instantiating addrmaps within regfiles is not '\
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'supported. Addrmaps shall be instantiated at the '\
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'top-level of other addrmaps')
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sys.exit(1)
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elif isinstance(child, node.RegfileNode):
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self.obj.current_idx = [0]
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new_child = RegFile(
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obj=child,
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parents_dimensions=self.total_array_dimensions,
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parents_strides=self.total_stride,
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config=config,
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glbl_settings=glbl_settings)
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self.regfiles[child.inst_name] = new_child
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elif isinstance(child, node.RegNode):
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if child.inst.is_alias:
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# If the node we found is an alias, we shall not create a
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# new register. Rather, we bury up the old register and add
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# additional properties
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self.registers[child.inst.alias_primary_inst.inst_name]\
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.add_alias(child)
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else:
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self.obj.current_idx = [0]
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new_child = Register(
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obj=child,
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parents_dimensions=self.total_array_dimensions,
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parents_strides=self.total_stride,
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config=config,
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glbl_settings=glbl_settings)
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self.registers[child.inst_name] = new_child
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try:
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if (regwidth := new_child.get_regwidth()) > self.regwidth:
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self.regwidth = regwidth
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except KeyError:
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# Simply ignore nodes like SignalNodes
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pass
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# Add registers to children. This must be done in a last step
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# to account for all possible alias combinations
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self.children = {**self.regfiles, **self.registers}
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# Create RTL of all registers
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[x.create_rtl() for x in self.registers.values()]
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self.logger.info("Done generating all child-regfiles/registers")
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# If this regfile create a generate-block, all the register's wires must
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# be declared outside of that block
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if self.generate_initiated:
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self.rtl_header = [*self.rtl_header, *self.get_signal_instantiations_list()]
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self.rtl_header.append("")
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self.rtl_header.append("generate")
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# Add description, if applicable
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self.rtl_header = [
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self.get_description(),
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*self.rtl_header
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]
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# Create comment and provide user information about register he/she
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# is looking at.
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self.rtl_header = [
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self._process_yaml(
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RegFile.templ_dict['regfile_comment'],
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{'name': obj.inst_name,
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'dimensions': self.own_dimensions,
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'depth': self.own_depth}
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),
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*self.rtl_header
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]
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# Create generate block for register and add comment
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for i in range(self.own_dimensions-1, -1, -1):
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self.rtl_footer.append(
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self._process_yaml(
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RegFile.templ_dict['generate_for_end'],
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{'dimension': ''.join(['gv_', chr(97+i)])}
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)
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)
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for i in range(self.own_dimensions):
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self.rtl_header.append(
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self._process_yaml(
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RegFile.templ_dict['generate_for_start'],
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{'iterator': ''.join(['gv_', chr(97+i+self.parents_depths)]),
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'limit': self.own_array_dimensions[i]}
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)
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)
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# End generate loop
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if self.generate_initiated:
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glbl_settings['generate_active'] = False
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self.rtl_footer.append("endgenerate")
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self.rtl_footer.append("")
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def create_mux_string(self):
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for i in self.children.values():
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yield from i.create_mux_string()
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def get_signal_instantiations_list(self) -> set():
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instantiations = []
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for child in self.children.values():
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if isinstance(child, Register):
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instantiations.append(f"\n// Variables of register '{child.name}'")
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instantiations = [*instantiations, *child.get_signal_instantiations_list()]
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return instantiations
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def get_package_names(self) -> set():
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names = set()
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for register in self.registers.values():
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for typedef in register.get_typedefs().values():
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names.add(typedef.scope)
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return names
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def get_package_rtl(self) -> {}:
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if not self.config['enums']:
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return None
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# First go through all registers in this scope to generate a package
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enum_rtl = {}
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# Need to keep track of enum names since they shall be unique
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# per scope
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enum_members = {}
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for register in self.registers.values():
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for key, value in register.get_typedefs().items():
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if value.scope not in enum_rtl:
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enum_rtl[value.scope] = []
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variable_list = []
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max_name_width = min(
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max([len(x[0]) for x in value.members]), 40)
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for var in value.members:
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if var[0] not in enum_members:
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enum_members[var[0]] = "::".join([self.name, key])
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else:
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self.logger.fatal(
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f"Enum member '{var[0]}' was found at multiple locations in the same "\
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"main scope: \n"\
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f" -- 1st occurance: '{enum_members[var[0]]}'\n"\
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f" -- 2nd occurance: '{'::'.join([self.name, key])}'\n\n"\
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"This is not legal because all these enums will be defined "\
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"in the same SystemVerilog scope. To share the same enum among "\
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"different registers, define them on a higher level in the "\
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"hierarchy.\n\n"\
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"Exiting...")
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sys.exit(1)
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variable_list.append(
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RegFile.templ_dict['enum_var_list_item']['rtl'].format(
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value = var[1],
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width = value.width,
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max_name_width = max_name_width,
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name = var[0]))
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enum_rtl[value.scope].append(
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RegFile.templ_dict['enum_declaration']['rtl'].format(
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width=value.width-1,
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name = key,
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enum_var_list = ',\n'.join(variable_list)))
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return enum_rtl
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