162 lines
5.4 KiB
YAML
162 lines
5.4 KiB
YAML
---
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access_wire_comment:
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rtl: |-
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// Register-activation for '{path}' {alias}
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access_wire_assign_1_dim:
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rtl: |-
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assign {path}_active = widget_if.addr == {addr};
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signals:
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- name: '{path}_active'
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signal_type: 'logic'
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access_wire_assign_multi_dim:
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rtl: |-
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assign {path}_active{genvars} = widget_if.addr == {addr}+({genvars_sum});
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signals:
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- name: '{path}_active'
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signal_type: 'logic'
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read_wire_assign:
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rtl: |-
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assign {path}_sw_rd{genvars} = {path}_active{genvars} && widget_if.r_vld;
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signals:
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- name: '{path}_sw_rd'
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signal_type: 'logic'
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read_wire_assign_0:
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rtl: |-
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assign {path}_sw_rd{genvars} = 0;
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signals:
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- name: '{path}_sw_rd'
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signal_type: 'logic'
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write_wire_assign:
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rtl: |-
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assign {path}_sw_wr{genvars} = {path}_active{genvars} && widget_if.w_vld;
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signals:
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- name: '{path}_sw_wr'
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signal_type: 'logic'
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write_wire_assign_0:
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rtl: |-
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assign {path}_sw_wr{genvars} = 0;
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signals:
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- name: '{path}_sw_wr'
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signal_type: 'logic'
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rw_wire_assign_any_alias:
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rtl: |-
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// Combined register activation. These will become active
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assign {path}__any_alias_sw_rd{genvars} = {sw_rds_w_genvars};
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assign {path}__any_alias_sw_wr{genvars} = {sw_wrs_w_genvars};
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signals:
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- name: '{path}__any_alias_sw_rd'
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signal_type: 'logic'
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- name: '{path}__any_alias_sw_wr'
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signal_type: 'logic'
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reg_comment: |-
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/*******************************************************************
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/*******************************************************************
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/* REGISTER : {name}
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/* DIMENSION : {dimensions}
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/* DEPTHS (per dimension): {depth}
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/*******************************************************************
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/*******************************************************************/
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description:
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rtl: |-
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/**REGISTER DESCRIPTION*********************************************
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{desc}
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/*******************************************************************/
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generate_for_start: |-
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for ({iterator} = 0; {iterator} < {limit}; {iterator}++)
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begin
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generate_for_end: |-
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end // of for loop with iterator {dimension}
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signal_declaration: |-
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{type:{signal_width}} {name:{name_width}}{unpacked_dim};
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sw_data_assignment_var_name:
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rtl: |-
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{path}_data_mux_in
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signals:
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- name: '{path}_data_mux_in'
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signal_type: 'logic [{accesswidth}:0]'
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sw_err_assignment_var_name:
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rtl: |-
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{path}_err_mux_in
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signals:
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- name: '{path}_err_mux_in'
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signal_type: 'logic'
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sw_rdy_assignment_var_name:
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rtl: |-
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{path}_rdy_mux_in
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signals:
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- name: '{path}_rdy_mux_in'
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signal_type: 'logic'
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sw_err_condition:
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rtl: |-
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!((widget_if.r_vld && ({rd_byte_list_ored})) || (widget_if.w_vld && ({wr_byte_list_ored})))
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sw_data_assignment:
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rtl: |-
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/**************************************
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* Assign all fields to signal to Mux *
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**************************************/
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// Assign all fields. Fields that are not readable are tied to 0.
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assign {sw_data_assignment_var_name}{genvars} = {{{list_of_fields}}};
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// Internal registers are ready immediately
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assign {sw_rdy_assignment_var_name}{genvars} = {rdy_condition};
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// Return an error if *no* read and *no* write was succesful. If some bits
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// cannot be read/written but others are succesful, don't return and error
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// Hence, as long as one action can be succesful, no error will be returned.
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assign {sw_err_assignment_var_name}{genvars} = {err_condition};
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external_rtl_wr:
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rtl: |-
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// This output will be asserted once a read is requested and will
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// stay high until '{path}_ext_w_ack' gets set.
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assign {path}_ext_wr_req{genvars} = reg_ext1_sw_wr{genvars};
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output_ports:
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- name: '{path}_ext_wr_req'
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signal_type: 'logic'
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external_rtl_rd:
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rtl: |-
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// This output will be asserted once a read is requested and will
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// stay high until '{path}_ext_r_ack' gets set.
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assign {path}_ext_rd_req{genvars} = reg_ext1_sw_rd{genvars};
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output_ports:
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- name: '{path}_ext_rd_req'
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signal_type: 'logic'
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external_rdy_condition:
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rtl: |-
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{path}_ext_{rd_or_wr}_ack{genvars}
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input_ports:
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- name: '{path}_ext_{rd_or_wr}_ack'
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signal_type: 'logic'
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external_err_condition:
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rtl: |-
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({path}_ext_{rd_or_wr}_err{genvars} && {path}_ext_{rd_or_wr}_ack{genvars} && widget_if.{rd_or_wr}_vld)
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input_ports:
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- name: '{path}_ext_{rd_or_wr}_err'
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signal_type: 'logic'
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- name: '{path}_ext_{rd_or_wr}_ack'
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signal_type: 'logic'
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interrupt_comment:
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rtl: |-
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/**************************************
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* Register contains interrupts *
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**************************************/
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interrupt_intr:
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rtl: |-
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// Register has at least one interrupt field
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assign {path}_intr{genvars} = |({list});
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output_ports:
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- name: '{path}_intr'
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signal_type: 'logic'
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interrupt_halt:
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rtl: |-
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// Register has at least one interrupt field with halt property set
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assign {path}_halt{genvars} = |({list});
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output_ports:
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- name: '{path}_halt'
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signal_type: 'logic'
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