mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-12-22 06:58:41 +00:00
Dennis
6359883c27
The software is now able to create most interrupt combinations of Section 9.9 of the SystemRDL 2.0 LRM. It supports stickybit/non-stickybit interrupts, it support posedge, negedge, bothedge, and level interrupts, and it is able to generate all surrounding logic. This commit also fixes a reset-bug that caused registers that were reset to 0 to be not reset (because 'if not reset_value' will return True if the 'reset_value' is 0). |
||
|---|---|---|
| .. | ||
| external_registers.rdl | ||
| interrupts.rdl | ||
| simple_rw_reg.rdl | ||