71 lines
1.3 KiB
YAML
71 lines
1.3 KiB
YAML
---
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module_declaration:
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rtl: |-
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module {name}
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<<INDENT>>
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{import_package_list}
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<<UNINDENT>>
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(
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<<INDENT>>
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// Clock & Resets
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input reg_clk,
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input bus_clk,
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input bus_rst_n,
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{resets}
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// Bus I/O
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// TODO
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// Inputs
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{inputs}
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// Outputs
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{outputs}
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<<UNINDENT>>
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);
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import_package:
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rtl: |-
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import {name}_pkg::*;
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reset_port:
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rtl:
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input {name},
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input_port:
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rtl:
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input {signal_type:{signal_width}} {name:{name_width}}{unpacked_dim},
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output_port:
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rtl:
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output {signal_type:{signal_width}} {name:{name_width}}{unpacked_dim},
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signal_declaration: |-
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{type:{signal_width}} {name:{name_width}}{unpacked_dim};
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package_declaration:
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rtl: |-
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package {name}_pkg;
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{pkg_content}
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endpackage
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enum_declaration:
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rtl: |-
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typedef enum logic [{width}:0] {{
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{enum_var_list}
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}} {name};
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enum_var_list_item:
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rtl: |-
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{name:{max_name_width}} = {width}'d{value}
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read_mux:
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rtl: |-
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// Read multiplexer
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always_comb
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begin
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case(addr)
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{list_of_cases}
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endcase
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end
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default_mux_case:
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rtl: |-
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default: sw_rd_bus = 0;
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list_of_mux_cases:
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rtl: |-
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32'd{}: sw_rd_bus = {};
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