srdl2sv/srdl2sv/components/templates/register.yaml

---
access_wire_comment:
    rtl: |-

        // Register-activation for '{path}' {alias}
access_wire_assign_1_dim:
    rtl: |-
        assign {path}_active = widget_if.addr == {addr};        
    signals:
        - name: '{path}_active'
          signal_type: 'logic'
access_wire_assign_multi_dim:
    rtl: |-
        assign {path}_active{genvars} = widget_if.addr == {addr}+({genvars_sum});        
    signals:
        - name: '{path}_active'
          signal_type: 'logic'
read_wire_assign: 
    rtl: |-
        assign {path}_sw_rd{genvars} = {path}_active{genvars} && widget_if.r_vld;        
    signals:
        - name: '{path}_sw_rd'
          signal_type: 'logic'
read_wire_assign_0: 
    rtl: |-
        assign {path}_sw_rd{genvars} = 0;        
    signals:
        - name: '{path}_sw_rd'
          signal_type: 'logic'
write_wire_assign: 
    rtl: |-
        assign {path}_sw_wr{genvars} = {path}_active{genvars} && widget_if.w_vld;        
    signals:
        - name: '{path}_sw_wr'
          signal_type: 'logic'
write_wire_assign_0: 
    rtl: |-
        assign {path}_sw_wr{genvars} = 0;        
    signals:
        - name: '{path}_sw_wr'
          signal_type: 'logic'
rw_wire_assign_any_alias:
    rtl: |-

        // Combined register activation. These will become active 
        assign {path}__any_alias_sw_rd{genvars} = {sw_rds_w_genvars};
        assign {path}__any_alias_sw_wr{genvars} = {sw_wrs_w_genvars};
    signals:
        - name: '{path}__any_alias_sw_rd'
          signal_type: 'logic'
        - name: '{path}__any_alias_sw_wr'
          signal_type: 'logic'
reg_comment: |-

    /*******************************************************************
    /*******************************************************************
    /* REGISTER              : {name}
    /* DIMENSION             : {dimensions}
    /* DEPTHS (per dimension): {depth}
    /*******************************************************************
    /*******************************************************************/
reg_desc: 
    rtl: |-

      /**REGISTER DESCRIPTION*********************************************
      {desc}
      /*******************************************************************/
generate_for_start: |-
    for ({iterator} = 0; {iterator} < {limit}; {iterator}++)
    begin    
generate_for_end: |-
    end // of for loop with iterator {dimension}    
signal_declaration: |-
    {type:{signal_width}} {name:{name_width}}{unpacked_dim};    
sw_data_assignment_var_name:
    rtl: |-
        {path}_data_mux_in        
    signals:
        - name: '{path}_data_mux_in'
          signal_type: 'logic [{accesswidth}:0]'
sw_err_assignment_var_name:
    rtl: |-
        {path}_err_mux_in        
    signals:
        - name: '{path}_err_mux_in'
          signal_type: 'logic'
sw_rdy_assignment_var_name:
    rtl: |-
        {path}_rdy_mux_in        
    signals:
        - name: '{path}_rdy_mux_in'
          signal_type: 'logic'
sw_err_condition:
    rtl: |-
        !((widget_if.r_vld && ({rd_byte_list_ored})) || (widget_if.w_vld && ({wr_byte_list_ored})))        
sw_data_assignment:
    rtl: |-

       /************************************** 
        * Assign all fields to signal to Mux *
        **************************************/
       // Assign all fields. Fields that are not readable are tied to 0.
       assign {sw_data_assignment_var_name}{genvars} = {{{list_of_fields}}};

       // Internal registers are ready immediately
       assign {sw_rdy_assignment_var_name}{genvars} = {rdy_condition};

       // Return an error if *no* read and *no* write was succesful. If some bits
       // cannot be read/written but others are succesful, don't return and error
       // Hence, as long as one action can be succesful, no error will be returned.
       assign {sw_err_assignment_var_name}{genvars} = {err_condition};
external_rtl_wr:
    rtl: |-
        // This output will be asserted once a read is requested and will
        // stay high until '{path}_ext_w_ack' gets set.
        assign {path}_ext_wr_req{genvars} = reg_ext1_sw_wr{genvars};        
    output_ports:
        - name: '{path}_ext_wr_req'
          signal_type: 'logic'
external_rtl_rd:
    rtl: |-
        // This output will be asserted once a read is requested and will
        // stay high until '{path}_ext_r_ack' gets set.
        assign {path}_ext_rd_req{genvars} = reg_ext1_sw_rd{genvars};        
    output_ports:
        - name: '{path}_ext_rd_req'
          signal_type: 'logic'
external_rdy_condition:
    rtl: |-
        {path}_ext_{rd_or_wr}_ack{genvars}        
    input_ports:
        - name: '{path}_ext_{rd_or_wr}_ack'
          signal_type: 'logic'
external_err_condition:
    rtl: |-
        ({path}_ext_{rd_or_wr}_err{genvars} && {path}_ext_{rd_or_wr}_ack{genvars} && widget_if.{rd_or_wr}_vld)        
    input_ports:
        - name: '{path}_ext_{rd_or_wr}_err'
          signal_type: 'logic'
        - name: '{path}_ext_{rd_or_wr}_ack'
          signal_type: 'logic'
interrupt_comment:
    rtl: |-
       /************************************** 
        * Register contains interrupts    *
        **************************************/       
interrupt_intr:
    rtl: |-
        // Register has at least one interrupt field
        assign {path}_intr{genvars} = |({list});        
    output_ports:
        - name: '{path}_intr'
          signal_type: 'logic'
interrupt_halt:
    rtl: |-

        // Register has at least one interrupt field with halt property set
        assign {path}_halt{genvars} = |({list});
    output_ports:
        - name: '{path}_halt'
          signal_type: 'logic'