39 lines
1.5 KiB
YAML
39 lines
1.5 KiB
YAML
# This file only contains the instantiation of the module
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module_instantiation:
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rtl: |-
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/*******************************************************************
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* CPU Interface
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*******************************************************************/
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assign widget_if.addr = cpuif_address_i;
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assign widget_if.w_data = cpuif_data_i;
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assign widget_if.w_vld = cpuif_wr_vld_i;
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assign widget_if.r_vld = cpuif_rd_vld_i;
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assign widget_if.byte_en = {no_byte_enable} ? {{{bus_width_byte}{{1'b1}}}} : cpuif_byte_enable_i;
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assign cpuif_data_o = widget_if.r_data;
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assign cpuif_rdy_o = widget_if.rdy;
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assign cpuif_err_o = widget_if.err;
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signals:
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- name: 'widget_if'
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signal_type: 'srdl2sv_widget_if #(.ADDR_W ({addr_width}), .DATA_W({bus_width}). NO_BYTE_ENABLE({no_byte_enable}))'
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input_ports:
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- name: 'clk'
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signal_type: ''
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- name: 'cpuif_address_i'
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signal_type: '[{addr_width}-1:0]'
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- name: 'cpuif_wr_vld_i'
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signal_type: ''
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- name: 'cpuif_rd_vld_i'
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signal_type: ''
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- name: 'cpuif_data_i'
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signal_type: '[{bus_width}-1:0]'
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- name: 'cpuif_byte_enable_i'
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signal_type: '[{bus_width_byte}-1:0]'
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output_ports:
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- name: 'cpuif_err_o'
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signal_type: ''
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- name: 'cpuif_rdy_o'
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signal_type: ''
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- name: 'cpuif_data_o'
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signal_type: '[{bus_width}-1:0]'
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