78 lines
2.4 KiB
YAML
78 lines
2.4 KiB
YAML
# This file only contains the instantiation of the module
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module_instantiation:
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rtl: |-
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/*******************************************************************
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* AMBA 3 AHB Lite Widget
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* ======================
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* Naming conventions
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* - widget_if -> SystemVerilog interface to between widgets
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* and the internal srdl2sv registers.
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* - H* -> Signals as defined in AMBA3 AHB Lite
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* specification
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* - clk -> Clock that drives registers and the bus
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*******************************************************************/
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srdl2sv_amba3ahblite
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#(.FLOP_REGISTER_IF (0),
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.BUS_BITS ({bus_width}),
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.NO_BYTE_ENABLE ({no_byte_enable}))
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srdl2sv_amba3ahblite_inst
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(// Bus protocol
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.HRESETn,
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.HCLK (clk),
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.HADDR,
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.HWRITE,
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.HSIZE,
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.HPROT,
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.HTRANS,
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.HWDATA,
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.HSEL,
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.HREADYOUT,
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.HRESP,
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.HRDATA,
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// Interface to internal logic
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.widget_if);
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signals:
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signals:
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- name: 'widget_if'
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signal_type: 'srdl2sv_widget_if #(.ADDR_W ({addr_width}), .DATA_W({bus_width}))'
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input_ports:
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- name: 'clk'
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signal_type: ''
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group: 'General Clock'
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- name: 'HRESETn'
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signal_type: ''
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group: 'AHB Protocol'
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- name: 'HADDR'
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signal_type: '[31:0]'
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group: 'AHB Protocol'
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- name: 'HWRITE'
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signal_type: ''
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group: 'AHB Protocol'
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- name: 'HSIZE'
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signal_type: '[2:0]'
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group: 'AHB Protocol'
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- name: 'HPROT'
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signal_type: '[3:0]'
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group: 'AHB Protocol'
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- name: 'HTRANS'
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signal_type: '[1:0]'
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group: 'AHB Protocol'
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- name: 'HWDATA'
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signal_type: '[{bus_width}-1:0]'
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group: 'AHB Protocol'
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- name: 'HSEL'
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signal_type: ''
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group: 'AHB Protocol'
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output_ports:
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- name: 'HREADYOUT'
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signal_type: ''
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group: 'AHB Protocol'
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- name: 'HRESP'
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signal_type: ''
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group: 'AHB Protocol'
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- name: 'HRDATA'
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signal_type: '[{bus_width}-1:0]'
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group: 'AHB Protocol'
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