378 lines
14 KiB
Plaintext
378 lines
14 KiB
Plaintext
//------------------------------------------------------------
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// Block Level Interrupt Register
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//------------------------------------------------------------
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reg block_int_r {
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name = "Example Block Interrupt Register";
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desc = "This is an example of an IP Block with 3 int events. 2 of these
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are non-fatal and the third event multi_bit_ecc_error is fatal";
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default hw=w; // HW can Set int only
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default sw=rw; // SW can clear
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default woclr; // Clear is via writing a 1
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field {
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desc = "A Packet with a CRC Error has been received";
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level intr;
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} crc_error = 0x0;
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field {
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desc = "A Packet with an invalid length has been received";
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level intr;
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} len_error = 0x0;
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field {
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desc="An uncorrectable multi-bit ECC error has been received";
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level intr;
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} multi_bit_ecc_error = 0 ;
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field {
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desc="Master who was active when ECC Error Occurred";
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sticky;
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} active_ecc_master[7:4] = 0; // Example of multi-bit sticky field
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// This field is not an intr
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}; // End of Reg: block_int_r
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reg block_int_en_r {
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name = "Example Block Interrupt Enable Register";
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desc = "This is an example of an IP Block with 3 int events";
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default hw=na; // HW can't access the enables
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default sw=rw; // SW can control them
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field {
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desc = "Enable: A Packet with a CRC Error has been received";
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} crc_error = 0x1;
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field {
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desc = "Enable: A Packet with an invalid length has been received";
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} len_error = 0x1;
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field {
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desc = "Enable: A multi-bit error has been detected";
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} multi_bit_ecc_error = 0x0;
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}; // End of Reg: block_int_en_r
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reg block_halt_en_r {
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name = "Example Block Halt Enable Register";
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desc = "This is an example of an IP Block with 3 int events";
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default hw=na; // HW can't access the enables
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default sw=rw; // SW can control them
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field {
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desc = "Enable: A Packet with a CRC Error has been received";
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} crc_error = 0x0; // not a fatal error do not halt
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field {
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desc = "Enable: A Packet with an invalid length has been received";
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} len_error = 0x0; // not a fatal error do not halt
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field {
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desc = "Enable: A Packet with an invalid length has been received";
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} multi_bit_ecc_error = 0x1; // fatal error that will
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// cause device to halt
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}; // End of Reg: block_halt_en_r
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//------------------------------------------------------------
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// Master Interrupt Status Register
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//------------------------------------------------------------
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reg master_int_r {
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name = "Master Interrupt Status Register";
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desc = "This register contains the status of the 4 lower Module interrupts.
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Also an interrupt signal (myMasterInt) is generated which is the 'OR'
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of the four Module interrupts. A Halt signal is also generated which
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represents the bitwise or the masked/enabled halt bits";
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default nonsticky intr; // Unless we want to have to clear this separately
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// from the leaf intr this should be non sticky
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default hw=w; // HW normally won't want to access this but it could
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default sw=r; // Software can just read this. It clears the leaf intr's
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// to clear this
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field {
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desc = "An interrupt has occurred with ModuleD.
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Software must read the ModuleD Master Interrupt Register
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in order to determine the source of the interrupt.";
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} module_d_int[3:3] = 0x0;
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field {
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desc = "An interrupt has occurred with ModuleC.
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Software must read the ModuleC Master Interrupt Register
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in order to determine the source of the interrupt.";
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} module_c_int[2:2] = 0x0;
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field {
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desc = "An interrupt has occurred with ModuleB.
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Software must read the ModuleB Interrupt Register
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in order to determine the source of the interrupt.";
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} module_b_int[1:1] = 0x0;
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field {
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desc = "An interrupt has occurred with ModuleA.
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Software must read the ModuleA Master Interrupt Register
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in order to determine the source of the interrupt.";
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} module_a_int[0:0] = 0x0;
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};
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//
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// The following is the accompanying enable register. Since the combinatorial
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// logic for processing the interrupt is internal to the generated verilog,
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// there's no need for an external port - which is realized by assigning "na"
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// to the hw attribute of the specific field. This could have been defined as
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// a mask register just as easily...
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//
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//------------------------------------------------------------
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// Interrupt Enable Register
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//------------------------------------------------------------
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reg master_int_en_r {
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name = "Master Interrupt Enable Register";
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desc = "Configurable register used in order to enable the corresponding
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interrupts found in myMasterInt register.";
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default hw = na;
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default sw = rw;
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field {
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desc = "Interrupt enable for ModuleD Interrupts. 1 = enable, 0 = disable";
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} module_d_int_en[3:3] = 0x0;
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field {
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desc = "Interrupt enable for ModuleC Interrupts. 1 = enable, 0 = disable";
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} module_c_int_en[2:2] = 0x0;
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field {
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desc = "Interrupt enable for ModuleB Interrupts. 1 = enable, 0 = disable";
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} module_b_int_en[1:1] = 0x0;
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field {
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desc = "Interrupt enable for ModuleA Interrupts. 1 = enable, 0 = disable";
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} module_a_int_en[0:0] = 0x0;
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};
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//------------------------------------------------------------
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// Halt Enable Register
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//------------------------------------------------------------
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// The halt en is another enable or mask that could be used to generate an
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// alternate signal like a halt that represents a fatal error in the system or
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// some other event NOTE: It does not have to mean fatal as the name implies
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// its just another priority level for interrupts...
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reg master_halt_en_r {
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name = "Master Halt Enable Register";
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desc = "Configurable register used in order to enable the corresponding
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interrupts found in myMasterInt register.";
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default hw = na;
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default sw = rw;
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field {
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desc = "Halt enable for ModuleD Interrupts. 1 = enable, 0 = disable";
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} module_d_halt_en[3:3] = 0x0;
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field {
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desc = "Halt enable for ModuleC Interrupts. 1 = enable, 0 = disable";
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} module_c_halt_en[2:2] = 0x0;
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field {
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desc = "Halt enable for ModuleB Interrupts. 1 = enable, 0 = disable";
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} module_b_halt_en[1:1] = 0x0;
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field {
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desc = "Halt enable for ModuelA Interrupts. 1 = enable, 0 = disable";
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} module_a_halt_en[0:0] = 0x0;
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};
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//------------------------------------------------------------
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// Global Interrupt Status Register
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//------------------------------------------------------------
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// This takes the block int which feeds the master int and then distills it
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// down one more level so we end up with a single bit intr and single bit halt...
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//------------------------------------------------------------
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// Global Interrupt/Halt Enable Register
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//------------------------------------------------------------
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reg final_en_r {
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name = "My Final Enable Register";
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desc = "This enable allows all interrupts/halts to be suppressed
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with a single bit";
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default hw = na;
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default sw = rw;
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field {
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desc = "Global Interrupt Enable. 1 = enable, 0 = disable";
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} global_int_en = 0x0;
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field {
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desc = "Global Halt Enable. 1 = enable, 0 = disable";
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} global_halt_en = 0x0;
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};
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reg final_int_r {
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name = "My Final Int/Halt Register";
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desc = "This distills a lower level interrupts into a final bit than can be
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masked";
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default sw = r; // sw does not need to clear global_int
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// (global_int is of type final_int_r)
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// instead it clears itself when all master_int intr
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// bits get serviced
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default nonsticky intr;
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default hw = w; // w needed since dyn assign below implies interconnect to hw
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// global_int.global_int->next = master_int->intr;
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field {
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desc = "Global Interrupt";
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} global_int = 0x0;
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field {
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desc = "Global Halt";
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} global_halt = 0x0;
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};
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addrmap interrupt_hierarchy {
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signal { activelow; async; field_reset;} field_reset_n;
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name = "Sample ASIC Interrupt Registers";
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desc = "This register map is designed how one can use interrupt concepts
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effectively in SystemRDL";
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// Leaf Interrupts
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// Block A Registers
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block_int_r block_a_int; // Instance the Leaf Int Register
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block_int_en_r block_a_int_en; // Instance the corresponding Int Enable
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// Register
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block_halt_en_r block_a_halt_en; // Instance the corresponding halt enable
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// register
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// This block connects the int bits to their corresponding
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// int enables and halt enables
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//
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block_a_int.crc_error->enable = block_a_int_en.crc_error;
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block_a_int.len_error->enable = block_a_int_en.len_error;
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block_a_int.multi_bit_ecc_error->enable = block_a_int_en.multi_bit_ecc_error;
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block_a_int.crc_error->haltenable = block_a_halt_en.crc_error;
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block_a_int.len_error->haltenable = block_a_halt_en.len_error;
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block_a_int.multi_bit_ecc_error->haltenable = block_a_halt_en.multi_bit_ecc_error;
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// Block B Registers
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block_int_r block_b_int @0x100;
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block_int_en_r block_b_int_en;
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block_halt_en_r block_b_halt_en;
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block_b_int.crc_error->enable = block_b_int_en.crc_error;
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block_b_int.len_error->enable = block_b_int_en.len_error;
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block_b_int.multi_bit_ecc_error->enable = block_b_int_en.multi_bit_ecc_error;
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block_b_int.crc_error->haltenable = block_b_halt_en.crc_error;
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block_b_int.len_error->haltenable = block_b_halt_en.len_error;
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block_b_int.multi_bit_ecc_error->haltenable = block_b_halt_en.multi_bit_ecc_error;
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// Block C Registers
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block_int_r block_c_int @0x200;
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block_int_en_r block_c_int_en;
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block_halt_en_r block_c_halt_en;
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block_c_int.crc_error->enable = block_c_int_en.crc_error;
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block_c_int.len_error->enable = block_c_int_en.len_error;
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block_c_int.multi_bit_ecc_error->enable = block_c_int_en.multi_bit_ecc_error;
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block_c_int.crc_error->haltenable = block_c_halt_en.crc_error;
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block_c_int.len_error->haltenable = block_c_halt_en.len_error;
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block_c_int.multi_bit_ecc_error->haltenable = block_c_halt_en.multi_bit_ecc_error;
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// Block D Registers
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block_int_r block_d_int @0x300;
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block_int_en_r block_d_int_en;
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block_halt_en_r block_d_halt_en;
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block_d_int.crc_error->enable = block_d_int_en.crc_error;
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block_d_int.len_error->enable = block_d_int_en.len_error;
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block_d_int.multi_bit_ecc_error->enable = block_d_int_en.multi_bit_ecc_error;
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block_d_int.crc_error->haltenable = block_d_halt_en.crc_error;
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block_d_int.len_error->haltenable = block_d_halt_en.len_error;
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block_d_int.multi_bit_ecc_error->haltenable = block_d_halt_en.multi_bit_ecc_error;
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//
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// Master Interrupts
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//
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master_int_r master_int @0x01000;
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master_int_r master_halt;
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master_int_en_r master_int_en;
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master_halt_en_r master_halt_en;
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// Associate the INT’s with the EN’s
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master_int.module_d_int->enable = master_int_en.module_d_int_en;
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master_int.module_c_int->enable = master_int_en.module_c_int_en;
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master_int.module_b_int->enable = master_int_en.module_b_int_en;
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master_int.module_a_int->enable = master_int_en.module_a_int_en;
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// Associate the HALT’s with the EN’s
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master_halt.module_d_int->haltenable = master_halt_en.module_d_halt_en;
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master_halt.module_c_int->haltenable = master_halt_en.module_c_halt_en;
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master_halt.module_b_int->haltenable = master_halt_en.module_b_halt_en;
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master_halt.module_a_int->haltenable = master_halt_en.module_a_halt_en;
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// Now hook the lower level leaf interrupts to the higher level interrupts
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// This connects the Implicit Or from Block A's INT reg after
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// masking/enable to the next level up (master)
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master_int.module_a_int->next = block_a_int->intr;
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// This connects the Implicit Or from Block B's INT reg after
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// masking/enable to the next level up (master)
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master_int.module_b_int->next = block_b_int->intr;
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// This connects the Implicit Or from Block C's INT reg after
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// masking/enable to the next level up (master)
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master_int.module_c_int->next = block_c_int->intr;
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// This connects the Implicit Or from Block D's INT reg after
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// masking/enable to the next level up (master)
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master_int.module_d_int->next = block_d_int->intr;
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// This connects the Implicit Or from Block A's HALT reg after
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// masking/enable to the next level up (master)
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master_halt.module_a_int->next = block_a_int->halt;
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// This connects the Implicit Or from Block B's HALT reg after
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// masking/enable to the next level up (master)
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master_halt.module_b_int->next = block_b_int->halt;
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// This connects the Implicit Or from Block C's HALT reg after
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// masking/enable to the next level up (master)
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master_halt.module_c_int->next = block_c_int->halt;
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// This connects the Implicit Or from Block D's HALT reg after
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// masking/enable to the next level up (master)
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master_halt.module_d_int->next = block_d_int->halt;
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final_int_r global_int @0x1010;
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// Inst the global int/halt register
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final_en_r global_int_en @0x1014;
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// Inst the global int/halt enable register
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global_int.global_int->enable = global_int_en.global_int_en;
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// Associate the INT with the EN
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global_int.global_halt->haltenable = global_int_en.global_halt_en;
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// Associate the HALT with the EN
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global_int.global_int->next = master_int->intr;
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// Take the or of the 4 blocks in the master
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// Int and create one final interrupt
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global_int.global_halt->next = master_halt->halt;
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// Take the or of the 4 blocks in the master
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// Int and create one final halt
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};
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