487 lines
18 KiB
Systemverilog
487 lines
18 KiB
Systemverilog
/*****************************************************************
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*
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* ███████╗██████╗ ██████╗ ██╗ ██████╗ ███████╗██╗ ██╗
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* ██╔════╝██╔══██╗██╔══██╗██║ ╚════██╗██╔════╝██║ ██║
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* ███████╗██████╔╝██║ ██║██║ █████╔╝███████╗██║ ██║
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* ╚════██║██╔══██╗██║ ██║██║ ██╔═══╝ ╚════██║╚██╗ ██╔╝
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* ███████║██║ ██║██████╔╝███████╗███████╗███████║ ╚████╔╝
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* ╚══════╝╚═╝ ╚═╝╚═════╝ ╚══════╝╚══════╝╚══════╝ ╚═══╝
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*
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* The present RTL was generated by srdl2sv v0.01. The RTL and all
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* templates the RTL is derived from are licensed under the MIT
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* license. The license is shown below.
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*
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* srdl2sv itself is licensed under GPLv3.
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*
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* Maintainer : Dennis Potter <dennis@dennispotter.eu>
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* Report Bugs: https://github.com/Silicon1602/srdl2sv/issues
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*
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* ===GENERATION INFORMATION======================================
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*
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* Generation information:
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* - User: : dpotter
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* - Time : November 06 2021 22:46:49
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* - Path : /home/dpotter/srdl2sv/examples/aliases
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* - RDL file : ['aliases.rdl']
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* - Hostname : ArchXPS
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*
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* RDL include directories:
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* -
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*
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* Commandline arguments to srdl2sv:
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* - Ouput Directory : srdl2sv_out
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* - Stream Log Level : INFO
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* - File Log Level : NONE
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* - Use Real Tabs : False
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* - Tab Width : 4
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* - Enums Enabled : True
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* - Address Errors : True
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* - Unpacked I/Os : True
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* - Register Bus Type: amba3ahblite
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* - Address width : 32
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* - Byte enables : True
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* - Descriptions : {'AddrMap': True, 'RegFile': True, 'Memory': True, 'Register': True, 'Field': True}
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*
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* ===LICENSE OF ALIASES.SV=====================================
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*
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* Copyright 2021 Dennis Potter <dennis@dennispotter.eu>
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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****************************************************************/
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module aliases
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(
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// Resets
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// Inputs
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input clk ,
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input HRESETn ,
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input [31:0] HADDR ,
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input HWRITE ,
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input [2:0] HSIZE ,
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input [3:0] HPROT ,
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input [1:0] HTRANS ,
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input [32-1:0] HWDATA ,
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input HSEL ,
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input [0:0] event1__some_event_in ,
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input four_field_reg__f1_hw_wr,
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input [7:0] four_field_reg__f1_in ,
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input four_field_reg__f2_hw_wr,
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input [7:0] four_field_reg__f2_in ,
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input four_field_reg__f3_hw_wr,
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input [7:0] four_field_reg__f3_in ,
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input four_field_reg__f4_hw_wr,
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input [7:0] four_field_reg__f4_in ,
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// Outputs
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output HREADYOUT ,
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output HRESP ,
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output [32-1:0] HRDATA ,
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output event1_intr ,
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output [7:0] four_field_reg__f1_r ,
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output [7:0] four_field_reg__f2_r ,
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output [7:0] four_field_reg__f3_r ,
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output reg four_field_reg__f3_swmod,
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output [7:0] four_field_reg__f4_r
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);
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// Internal signals
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srdl2sv_widget_if #(.ADDR_W (32), .DATA_W(32)) widget_if;
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/*******************************************************************
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* AMBA 3 AHB Lite Widget
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* ======================
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* Naming conventions
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* - widget_if -> SystemVerilog interface to between widgets
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* and the internal srdl2sv registers.
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* - H* -> Signals as defined in AMBA3 AHB Lite
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* specification
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* - clk -> Clock that drives registers and the bus
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*******************************************************************/
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srdl2sv_amba3ahblite
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#(.FLOP_REGISTER_IF (0),
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.BUS_BITS (32),
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.NO_BYTE_ENABLE (0))
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srdl2sv_amba3ahblite_inst
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(// Bus protocol
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.HRESETn,
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.HCLK (clk),
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.HADDR,
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.HWRITE,
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.HSIZE,
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.HPROT,
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.HTRANS,
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.HWDATA,
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.HSEL,
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.HREADYOUT,
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.HRESP,
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.HRDATA,
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// Interface to internal logic
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.widget_if);
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/*******************************************************************
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/*******************************************************************
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/* REGISTER : event1
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/* DIMENSION : 0
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/* DEPTHS (per dimension): []
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/*******************************************************************
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/*******************************************************************/
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/**REGISTER DESCRIPTION*********************************************
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This register shows the alias example from Section 10.5.2 of the
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SystemRDL2.0 spec (with some slight adaptations to make it compilable).
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/*******************************************************************/
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logic event1_active ;
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logic event1_sw_wr ;
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logic event1_for_dv_active ;
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logic event1_for_dv_sw_wr ;
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logic [31:0] event1_data_mux_in ;
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logic event1_rdy_mux_in ;
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logic event1_err_mux_in ;
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logic [31:0] event1_for_dv_data_mux_in ;
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logic event1_for_dv_rdy_mux_in ;
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logic event1_for_dv_err_mux_in ;
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logic [0:0] event1__some_event_sticky_latch;
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logic [0:0] event1__some_event_q ;
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// Register-activation for 'event1'
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assign event1_active = widget_if.addr == 0;
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assign event1_sw_wr = event1_active && widget_if.w_vld;
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// Register-activation for 'event1_for_dv' (alias)
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assign event1_for_dv_active = widget_if.addr == 4;
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assign event1_for_dv_sw_wr = event1_for_dv_active && widget_if.w_vld;
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//-----------------FIELD SUMMARY-----------------
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// name : some_event (event1[0:0])
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// access : hw = w
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// sw = rw (precedence)
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// reset : - / -
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// flags : ['intr', 'intr type', 'sw', 'woclr']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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begin
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if (event1_sw_wr)
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begin
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if (widget_if.byte_en[0]) // woclr property
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event1__some_event_q[0:0] <= event1__some_event_q[0:0] & ~widget_if.w_data[0:0];
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end
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else
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if (event1_for_dv_sw_wr)
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begin
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if (widget_if.byte_en[0]) // woset property
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event1__some_event_q[0:0] <= event1__some_event_q[0:0] | widget_if.w_data[0:0];
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end
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else
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begin
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for (int i = 0; i < 1; i++)
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begin
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if (event1__some_event_sticky_latch[i])
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begin
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// Stickybit. Keep value until software clears it
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event1__some_event_q[i] <= 1'b1;
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end
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end
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end
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end // of event1__some_event's always_ff
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// Define signal that causes the interrupt to be set (level-type interrupt)
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assign event1__some_event_sticky_latch = event1__some_event_in;
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/**************************************
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* Register contains interrupts *
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**************************************/
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// Register has at least one interrupt field
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assign event1_intr = |(event1__some_event_q);
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/**********************************************
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* Assign all fields to signal to Mux *
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**********************************************/
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// Assign all fields. Fields that are not readable are tied to 0.
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assign event1_data_mux_in = {{31{1'b0}}, event1__some_event_q};
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// Internal registers are ready immediately
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assign event1_rdy_mux_in = 1'b1;
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// Return an error if *no* read and *no* write was succesful. If some bits
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// cannot be read/written but others are succesful, don't return and error
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// Hence, as long as one action can be succesful, no error will be returned.
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assign event1_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0])) || (widget_if.w_vld && (widget_if.byte_en[0])));
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/**********************************************
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* Assign all fields to signal to Mux (alias) *
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**********************************************/
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// Assign all fields. Fields that are not readable are tied to 0.
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assign event1_for_dv_data_mux_in = {{31{1'b0}}, event1__some_event_q};
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// Internal registers are ready immediately
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assign event1_for_dv_rdy_mux_in = 1'b1;
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// Return an error if *no* read and *no* write was succesful. If some bits
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// cannot be read/written but others are succesful, don't return and error
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// Hence, as long as one action can be succesful, no error will be returned.
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assign event1_for_dv_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0])) || (widget_if.w_vld && (widget_if.byte_en[0])));
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/*******************************************************************
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/*******************************************************************
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/* REGISTER : four_field_reg
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/* DIMENSION : 0
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/* DEPTHS (per dimension): []
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/*******************************************************************
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/*******************************************************************/
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/**REGISTER DESCRIPTION*********************************************
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This is a register with 4 fields.
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/*******************************************************************/
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logic four_field_reg_active ;
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logic four_field_reg_sw_wr ;
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logic two_field_alias_active ;
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logic two_field_alias_sw_wr ;
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logic four_field_reg__any_alias_sw_wr;
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logic [31:0] four_field_reg_data_mux_in ;
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logic four_field_reg_rdy_mux_in ;
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logic four_field_reg_err_mux_in ;
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logic [31:0] two_field_alias_data_mux_in ;
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logic two_field_alias_rdy_mux_in ;
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logic two_field_alias_err_mux_in ;
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logic [7:0] four_field_reg__f1_q ;
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logic [7:0] four_field_reg__f2_q ;
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logic [7:0] four_field_reg__f3_q ;
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logic [7:0] four_field_reg__f4_q ;
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// Register-activation for 'four_field_reg'
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assign four_field_reg_active = widget_if.addr == 8;
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assign four_field_reg_sw_wr = four_field_reg_active && widget_if.w_vld;
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// Register-activation for 'two_field_alias' (alias)
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assign two_field_alias_active = widget_if.addr == 12;
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assign two_field_alias_sw_wr = two_field_alias_active && widget_if.w_vld;
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// Combined register activation. These will become active on
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// access via any of the alias registers.
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assign four_field_reg__any_alias_sw_wr = four_field_reg_sw_wr || two_field_alias_sw_wr;
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//-----------------FIELD SUMMARY-----------------
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// name : f1 (four_field_reg[7:0])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : ['sw', 'wel']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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begin
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if (four_field_reg_sw_wr)
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begin
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if (widget_if.byte_en[0])
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four_field_reg__f1_q[7:0] <= widget_if.w_data[7:0];
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end
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else
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if (two_field_alias_sw_wr)
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begin
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if (widget_if.byte_en[0])
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four_field_reg__f1_q[7:0] <= widget_if.w_data[7:0];
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end
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else
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if (!four_field_reg__f1_hw_wr)
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four_field_reg__f1_q <= four_field_reg__f1_in;
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end // of four_field_reg__f1's always_ff
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// Connect register to hardware output port
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assign four_field_reg__f1_r = four_field_reg__f1_q;
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//-----------------FIELD SUMMARY-----------------
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// name : f2 (four_field_reg[15:8])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : ['sw', 'wel']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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begin
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if (four_field_reg_sw_wr)
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begin
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if (widget_if.byte_en[1])
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four_field_reg__f2_q[7:0] <= widget_if.w_data[15:8];
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end
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else
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if (!four_field_reg__f2_hw_wr)
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four_field_reg__f2_q <= four_field_reg__f2_in;
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end // of four_field_reg__f2's always_ff
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// Connect register to hardware output port
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assign four_field_reg__f2_r = four_field_reg__f2_q;
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//-----------------FIELD SUMMARY-----------------
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// name : f3 (four_field_reg[23:16])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : ['sw', 'wel', 'swmod']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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begin
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if (four_field_reg_sw_wr)
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begin
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if (widget_if.byte_en[2])
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four_field_reg__f3_q[7:0] <= widget_if.w_data[23:16];
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end
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else
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if (!four_field_reg__f3_hw_wr)
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four_field_reg__f3_q <= four_field_reg__f3_in;
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end // of four_field_reg__f3's always_ff
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// Connect register to hardware output port
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assign four_field_reg__f3_r = four_field_reg__f3_q;
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// Combinational block to generate swmod-output signals
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always_comb
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begin
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four_field_reg__f3_swmod = 0;
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four_field_reg__f3_swmod |= four_field_reg__any_alias_sw_wr && |widget_if.byte_en[2:2];
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end
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//-----------------FIELD SUMMARY-----------------
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// name : f4 (four_field_reg[31:24])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : ['sw', 'wel', 'rclr']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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begin
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if (four_field_reg_sw_wr)
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begin
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if (widget_if.byte_en[3])
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four_field_reg__f4_q[7:0] <= widget_if.w_data[31:24];
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end
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else
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if (two_field_alias_sw_wr)
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begin
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if (widget_if.byte_en[3]) // woclr property
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four_field_reg__f4_q[7:0] <= four_field_reg__f4_q[7:0] & ~widget_if.w_data[31:24];
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end
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else
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if (!four_field_reg__f4_hw_wr)
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four_field_reg__f4_q <= four_field_reg__f4_in;
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end // of four_field_reg__f4's always_ff
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// Connect register to hardware output port
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assign four_field_reg__f4_r = four_field_reg__f4_q;
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/**********************************************
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* Assign all fields to signal to Mux *
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**********************************************/
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// Assign all fields. Fields that are not readable are tied to 0.
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assign four_field_reg_data_mux_in = {four_field_reg__f4_q, four_field_reg__f3_q, four_field_reg__f2_q, four_field_reg__f1_q};
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// Internal registers are ready immediately
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assign four_field_reg_rdy_mux_in = 1'b1;
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// Return an error if *no* read and *no* write was succesful. If some bits
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// cannot be read/written but others are succesful, don't return and error
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// Hence, as long as one action can be succesful, no error will be returned.
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assign four_field_reg_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0])));
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/**********************************************
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* Assign all fields to signal to Mux (alias) *
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**********************************************/
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// Assign all fields. Fields that are not readable are tied to 0.
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assign two_field_alias_data_mux_in = {four_field_reg__f4_q, {16{1'b0}}, four_field_reg__f1_q};
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// Internal registers are ready immediately
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assign two_field_alias_rdy_mux_in = 1'b1;
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// Return an error if *no* read and *no* write was succesful. If some bits
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// cannot be read/written but others are succesful, don't return and error
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// Hence, as long as one action can be succesful, no error will be returned.
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assign two_field_alias_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[3] || widget_if.byte_en[0])) || (widget_if.w_vld && (widget_if.byte_en[3] || widget_if.byte_en[0])));
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// Read multiplexer
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always_comb
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begin
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unique case (1'b1)
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event1_active:
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begin
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widget_if.r_data = event1_data_mux_in;
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widget_if.err = event1_err_mux_in;
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widget_if.rdy = event1_rdy_mux_in;
|
|
end
|
|
event1_for_dv_active:
|
|
begin
|
|
widget_if.r_data = event1_for_dv_data_mux_in;
|
|
widget_if.err = event1_for_dv_err_mux_in;
|
|
widget_if.rdy = event1_for_dv_rdy_mux_in;
|
|
end
|
|
four_field_reg_active:
|
|
begin
|
|
widget_if.r_data = four_field_reg_data_mux_in;
|
|
widget_if.err = four_field_reg_err_mux_in;
|
|
widget_if.rdy = four_field_reg_rdy_mux_in;
|
|
end
|
|
two_field_alias_active:
|
|
begin
|
|
widget_if.r_data = two_field_alias_data_mux_in;
|
|
widget_if.err = two_field_alias_err_mux_in;
|
|
widget_if.rdy = two_field_alias_rdy_mux_in;
|
|
end
|
|
default:
|
|
begin
|
|
// If the address is not found, return an error
|
|
widget_if.r_data = 0;
|
|
widget_if.err = 1;
|
|
widget_if.rdy = widget_if.r_vld || widget_if.w_vld;
|
|
end
|
|
endcase
|
|
end
|
|
endmodule
|