A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
asic
systemverilog
systemrdl-compiler
systemrdl
registers
register-description-language
rdl
hdl
hardware-description-language
fpga
verilog
Updated 2021-11-27 00:53:06 +00:00
An extensible Python chatbot that is compatible with the Matrix protocol
Updated 2019-02-27 18:09:47 +00:00