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Dennis / srdl2sv
Python 0 0

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

asic
systemverilog
systemrdl-compiler
systemrdl
registers
register-description-language
rdl
hdl
hardware-description-language
fpga
verilog

Updated 2021-11-27 01:53:06 +01:00