Update PDF version of resume
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\end{tabular*}%
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}
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\newcommand*{\cventrytriple}[9]{%
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\cventrytriplecont
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\newcommand*{\cventrytriplecont}[4]{%
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{\entrypositionstyle{\tempa} & \\}
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{\entrypositionstyle{#1} & \entrydatestyle{#3} \entrydatestyle{//} \entrylocationstylesmall{#2}\\}
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\multicolumn{2}{L{\textwidth}}{\descriptionstyle{#4}}
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\end{tabular*}%
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}
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% Define an environment for cvsubentry
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\newenvironment{cvsubentries}{%
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\begin{center}
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\usepackage{fontspec}
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\newcommand*{\faicon}[1]{{
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\FA\csname faicon@#1\endcsname
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BIN
cv/resume.pdf
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cv/resume.pdf
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% Available options: circle|rectangle,edge/noedge,left/right
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% \photo[rectangle,edge,right]{./examples/profile}
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\name{Dennis}{Potter}
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\position{Electrical Engineer{\enskip\cdotp\enskip}Computer Scientist}
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\address{Malteserstrasse 16, 52062 Aachen, Germany}
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\position{Electrical Engineer{\enskip\cdotp\enskip}Computer Engineer}
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\address{1 Vista Montana \#2463, CA 95134 San Jose, USA}
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\mobile{(+49) 176 386 635 87}
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\mobile{1 408 908 8361}
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\email{dennis@dennispotter.eu}
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\homepage{dennispotter.eu}
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\linkedin{dennispotter25}
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@ -86,9 +86,9 @@
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%-------------------------------------------------------------------------------
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\input{resume/summary.tex}
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\input{resume/skills.tex}
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\input{resume/education.tex}
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\input{resume/experience.tex}
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\input{resume/extracurricular.tex}
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\input{resume/education.tex}
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%\input{resume/extracurricular.tex}
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%-------------------------------------------------------------------------------
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\end{document}
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@ -12,7 +12,7 @@
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%---------------------------------------------------------
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\cventrydouble
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{M.Sc. Electrical Engineering and Computer Science} % Degree
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{M.Sc. Electrical Engineering, Information Technology, \& Computer Engineering} % Degree
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{RWTH Aachen University} % Institution
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{Aachen (D)} % Location
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{Oct. 2015 - Nov. 2018} % Date(s)
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@ -20,10 +20,10 @@
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\begin{cvitems} % Description(s) bullet points
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\item \textit{Specialization}: Micro- and Nanoelectronics
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\item \textit{Final project}: ``Implementation and Analysis of RDMA Communication in a Real-Time Co-Simulation Framework"---An analysis and subsequent implementation of the Virtual Interface Architecture Infiniband, using the OpenStack verbs, in order to achieve high throughput and minimal latency between nodes of the real-time co-simulation framework VILLASnode.
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\item \textit{Modules included}: lectures on VLSI architectures, computer arithmetics, mixed analog signals, neural networks, new materials and devices in information technology, numerical device simulation, and operating systems. Lab training on VLSI design, FPGA programming in VHDL, and on the production of FeRAM cells.
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\item \textit{Modules included}: lectures on VLSI architectures, computer arithmetics, mixed analog signals, neural networks, new materials and devices in information technology, numerical device simulation, and operating systems. Lab trainings on full custom design, FPGA development, and on the production of FeRAM cells.
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\end{cvitems}
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}
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{B.Sc. Electrical Engineering and Computer Science} % Degree
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{B.Sc. Electrical Engineering, Information Technology, \& Computer Engineering} % Degree
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{Aachen (D)} % Location
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{Oct. 2011 - Sept. 2015} % Date(s)
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{
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@ -34,14 +34,11 @@
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%---------------------------------------------------------
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\cventry
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{Gymnasium} % Degree
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{Gymnasium (Comparable to a university-preparatory school with Latin as additional language.)} % Degree
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{Sophianum SG. in het Heuvelland} % Institution
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{Gulpen (NL)} % Location
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{Sept. 2005 - July. 2011} % Date(s)
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{
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\begin{cvitems} % Description(s) bullet points
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\item Comparable to a university-preparatory school with Latin as additional language.
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\end{cvitems}
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}
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%---------------------------------------------------------
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@ -7,19 +7,60 @@
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%-------------------------------------------------------------------------------
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% CONTENT
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%-------------------------------------------------------------------------------
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\vspace{-3.5mm}
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\vspace{-1.5mm}
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\begin{cventries}
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%---------------------------------------------------------
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\cventrydouble
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{Consultant} % Job title
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{Aquantia Corp.} % Organization
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{Aachen (D)} % Location
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{Aug. 2017 - Present} % Date(s)
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\cventry
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{Senior Staff Digital Design Engineer} % Job title
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{Marvell Semiconductor} % Organization
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{Santa Clara (USA)} % Location
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{Jul. 2021 - Present} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Development of a layer 2 Ethernet switch in SystemC. The goal was to create a transmission line model to verify functionality, which could be easily translated into synthesizable code later, using a high-level synthesis suite.
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\item Support and further development of the FPGA user interface and the power analysis environment which was developed during the internship.
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\item Owning a digital subsystem that provides MACsec (IEEE 802.3AE), PTP (IEEE 1588/IEEE 802.1AS), and MAC functionalities.
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\item Maintaining \& improving the proprietary Logic Analyser Module (LAM) hardware and software. Debugging silicon issues on various products with help of the proprietary LAM.
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\item Improving \& extending the previously designed front-end methodology. This includes, i.a., replacing underperforming EDA tools, using novel version control management techniques to improve user usability \& efficiency, adding automated regression tests to increase the (early) detection of bugs.
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\item Reviewing digital signal processing (DSP) hardware in a coherent optical DSP chip and developing the firmware for said hardware.
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\end{cvitems}
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}
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%---------------------------------------------------------
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\cventry
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{Staff Digital Design Engineer} % Job title
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{Marvell Semiconductor} % Organization
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{Aachen (D)} % Location
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{Oct. 2019 - Jul. 2021} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Owning a digital subsystem that provides MACsec (IEEE 802.3AE), PTP (IEEE 1588/IEEE 802.1AS), and MAC functionalities.
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\item Co-architecting and implementing a CSI module. This includes the encapsulation of pseudo-CSI2-packets into Ethernet packets with a configurable Ethernet/IP/UDP/AVTP header at the Rx-side of the block, and decapsulation and reordering of those packets at a Tx-side.
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\item Creating software to extract signals from a proprietary Logic Analyser Module and subsequently translating it to a VCD file that can be interpreted by any waveform viewer.
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\item Developing a script to automatically resolve congestion issues and Lint warnings in auto-generated register files.
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\item Debugging AHB bus issues in full chip simulations.
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\item Setting up a methodology for all front-end activity. This includes, i.a., the directory structure, version control management, regression management, RTL coding guidelines, and design libraries. Furthermore, convenient wrapper scripts that seemingly integrate in the flow for Cadence Joules, Spyglass Lint, Mentor CDC, Agnisys idsbatch, Cadence Conformal, and TSMC memories were written.
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\end{cvitems}
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}
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%---------------------------------------------------------
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\cventrytriple
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{Member of Technical Staff II} % Job title
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{Aquantia Corp.} % Organization
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{Aachen (D)} % Location
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{Dec. 2018 - Sept. 2019} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Designing a store \& forward Ethernet switch with a dynamic CAM, FRER (de)duplication, and seperate lanes for high- and low priority traffic.
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\item Creating a proprietary Logic Analyser Module to extract signals from the silicon chip. This includes cyclic buffering, triggering on (maskable) patterns, filtering (maskable) patterns, and compression.
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\item Developing a Python script to pre-process (hierarchical) Verilog Manifest files and sanity checking the included files.
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\end{cvitems}
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}
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{Contractor} % Job title
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{Aachen (D)} % Location
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{Aug. 2017 - Nov. 2018} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Developing a synthesizable layer 2 Ethernet switch in SystemC and evaluating DV \& synthesis capabilities of a high-level synthesis suite.
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\item Providing support for the FPGA GUI and the power analysis environment that was developed during the internship.
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\end{cvitems}
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}
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{Intern} % Job title
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{Nov. 2016 - July. 2017} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Creation of an automated power analysis environment, build on top of Ansys' PowerArtist. Subsequently, power analysis and reduction on various digital designs was done.
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\item Development of an intuitive graphical user interface, written in Python, Tkinter, and C, to access and manipulate an FPGA Ethernet debug tool.
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\item RTL power analysis and reduction on various digital designs using Ansys' PowerArtist.
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\item Developing an intuitive GUI—written in Python, Tkinter, and C—to control an FPGA Ethernet debug tool.
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\end{cvitems}
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}
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%---------------------------------------------------------
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\cventrydouble
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\cventry
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{Web developer and server administrator} % Job title
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{Boscafé 't Hijgend Hert} % Organization
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{Vijlen (NL)} % Location
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{Apr. 2012 - Mar. 2018} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Responsible for the online marketing, the development of several websites, and the maintenance and security of their Linux based virtual private server.
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\end{cvitems}
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}
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{Headwaiter} % Job title
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{Vijlen (NL)} % Location
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{Sept. 2010 - July. 2016} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Head of a small subteam of about 8 waiters. Responsible for a smooth running of daily restaurant business.
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\item Boscafé 't Hijgend Hert is a popular restaurant (500+ seats) \& tourist destination in the south of the Netherlands. Responsibilities included the restaurant's IT (including POS systems), the development of several websites, and the maintenance and security of their Linux based VPS.
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\end{cvitems}
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}
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%---------------------------------------------------------
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\cvskill
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{Programming \& Scripting} % Category
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{C, C++, Python, Rust, SystemC, (System)Verilog, Perl, Bash, MATLAB, PHP} % Skills
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{SystemVerilog, C, C++, Python, Rust, SystemC, Perl, TCL, Make, Bash, TCSH, MATLAB} % Skills
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%---------------------------------------------------------
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\cvskill
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%---------------------------------------------------------
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\cvskill
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{Miscellaneous} % Category
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{Ethernet, Infiniband, Linux, SQL, Tkinter} % Skills
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{Ethernet, MACsec, PTP, CSI2, RISC-V, Infiniband, Linux} % Skills
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%---------------------------------------------------------
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\cvskill
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{Languages} % Category
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{Dutch, German, English} % Skills
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{Dutch, English, German} % Skills
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%---------------------------------------------------------
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\end{cvskills}
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% CONTENT
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%-------------------------------------------------------------------------------
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\begin{cvparagraph}
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Currently working as engineering consultant for Aquantia Corp. Always curious about technological innovations and therefore graduated in electrical engineering \& computer science. Strives for a complete understanding of computers, from the lowest level---i.e., the bare integrated circuits---to the highest---i.e., user space---, and is therefore always eager to learn something new. Enjoys writing small programs in his free time, either to automate everyday problems, or simply for the sake of fun, and gets excited by the seemingly endless possibilities of Linux. Loves a good read, also on non-tech subjects like economics, anthropology, or (geo)politics.
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I am a senior staff engineer digital IC design at Marvell Semiconductor and have always been curious about technological innovations. For that reason I graduated in electrical engineering, information technology \& computer engineering. I have always striven for a complete understanding of computers, from the lowest level—i.e., the bare integrated circuits—to the highest—i.e., user space—and am therefore always eager to learn something new. I enjoy writing small programs in my free time, either to automate everyday problems, or simply for the sake of fun, and get excited by the seemingly endless possibilities of Linux. Furthermore, there is always time for a good read, also on non-tech subjects like economics, anthropology, or (geo)politics.
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%---------------------------------------------------------
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\end{cvparagraph}
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