srdl2sv/examples/simple_rw_reg/Makefile

RTL_TARGETS = $(subst .rdl,.sv,srdl2sv_out/$(shell ls *.rdl))

.PHONY: clean 

default: verilog_compile

verilog_compile: $(RTL_TARGETS)
	verilator -cc -sv $(shell ls srdl2sv_out/*.sv)

srdl2sv_out/%.sv: %.rdl $(shell which srdl2sv)
	srdl2sv $< --out-dir $(shell dirname $@) --stdout-logging INFO

clean:
	rm -rf srdl2sv_out
Add Makefiles in example/ to easily rebuild all examples 2021-10-31 23:38:27 +00:00			`RTL_TARGETS = $(subst .rdl,.sv,srdl2sv_out/$(shell ls *.rdl))`

			`.PHONY: clean`

Update Makefiles in examples directory to also invoke a Verilator compile 2021-11-05 06:38:50 +00:00			`default: verilog_compile`

			`verilog_compile: $(RTL_TARGETS)`
			`verilator -cc -sv $(shell ls srdl2sv_out/*.sv)`
Add Makefiles in example/ to easily rebuild all examples 2021-10-31 23:38:27 +00:00
Update example's Makefile to always rebuild if srdl2sv updates 2021-11-03 06:20:35 +00:00			`srdl2sv_out/%.sv: %.rdl $(shell which srdl2sv)`
			`srdl2sv $< --out-dir $(shell dirname $@) --stdout-logging INFO`
Add Makefiles in example/ to easily rebuild all examples 2021-10-31 23:38:27 +00:00
			`clean:`
			`rm -rf srdl2sv_out`