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Add default value to mux to prevent an inferred latch

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This commit is contained in:
Dennis Potter 2021-06-25 01:35:55 +02:00
parent ce4782c11d
commit 01a696c2b3
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 7 additions and 4 deletions
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6
srdl2sv/components/addrmap.py
View File

@ -176,19 +176,19 @@ class AddrMap(Component):
AddrMap.templ_dict['read_mux'], AddrMap.templ_dict['read_mux'],
{'list_of_cases': {'list_of_cases':
'\n'.join([ '\n'.join([
AddrMap.templ_dict['list_of_mux_cases']['rtl'] AddrMap.templ_dict['default_mux_case']['rtl'],
*[AddrMap.templ_dict['list_of_mux_cases']['rtl']
.format(x[0][1]+x[1][0], .format(x[0][1]+x[1][0],
''.join( ''.join(
[x[0][0], [x[0][0],
x[1][1]])) for y in self.children.values() \ x[1][1]])) for y in self.children.values() \
for x in y.create_mux_string() for x in y.create_mux_string()
]
]) ])
} }
) )
) )
def __add_signal_instantiation(self): def __add_signal_instantiation(self):
dict_list = [(key, value) for (key, value) in self.get_signals(True).items()] dict_list = [(key, value) for (key, value) in self.get_signals(True).items()]
signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40) signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)

3
srdl2sv/components/templates/addrmap.yaml
View File

@ -58,6 +58,9 @@ read_mux:
{list_of_cases} {list_of_cases}
endcase endcase
end end
default_mux_case:
rtl: |-
default: sw_rd_bus = 0;
list_of_mux_cases: list_of_mux_cases:
rtl: |- rtl: |-
32'd{}: sw_rd_bus = {}; 32'd{}: sw_rd_bus = {};