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https://github.com/Silicon1602/srdl2sv.git
synced 2024-11-14 11:03:36 +00:00
Add default value to mux to prevent an inferred latch
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parent
ce4782c11d
commit
01a696c2b3
@ -176,19 +176,19 @@ class AddrMap(Component):
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AddrMap.templ_dict['read_mux'],
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AddrMap.templ_dict['read_mux'],
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{'list_of_cases':
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{'list_of_cases':
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'\n'.join([
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'\n'.join([
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AddrMap.templ_dict['list_of_mux_cases']['rtl']
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AddrMap.templ_dict['default_mux_case']['rtl'],
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*[AddrMap.templ_dict['list_of_mux_cases']['rtl']
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.format(x[0][1]+x[1][0],
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.format(x[0][1]+x[1][0],
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''.join(
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''.join(
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[x[0][0],
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[x[0][0],
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x[1][1]])) for y in self.children.values() \
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x[1][1]])) for y in self.children.values() \
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for x in y.create_mux_string()
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for x in y.create_mux_string()
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]
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])
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])
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}
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}
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)
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)
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)
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)
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def __add_signal_instantiation(self):
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def __add_signal_instantiation(self):
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dict_list = [(key, value) for (key, value) in self.get_signals(True).items()]
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dict_list = [(key, value) for (key, value) in self.get_signals(True).items()]
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signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)
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signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)
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@ -58,6 +58,9 @@ read_mux:
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{list_of_cases}
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{list_of_cases}
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endcase
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endcase
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end
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end
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default_mux_case:
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rtl: |-
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default: sw_rd_bus = 0;
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list_of_mux_cases:
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list_of_mux_cases:
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rtl: |-
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rtl: |-
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32'd{}: sw_rd_bus = {};
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32'd{}: sw_rd_bus = {};
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