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Add very basic, incomplete statemachine for AHB protocol
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@ -26,19 +26,9 @@
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module srdl2sv_amba3ahblite
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import srdl2sv_if_pkg::*;
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#(
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parameter FLOP_IN = 0, // Set to '1' to flop input from the AHB bus. This is meant
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// to help meet timing. Don't use this to synchronize the input.
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parameter SYNC_IO = 0 // Set to '1' to in case HCLK and bus_clk are asynchronous
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// By default, mainly for it to directly work in simulations,
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// it will double-flops based on always_ff-blocks. To replace
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// this module with a proper MTBF-optimized double flop cell,
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// the contents of the synchronizer module `srdl2sv_sync.sv`
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// shall be updated
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parameter bit FLOP_REGISTER_IF = 0
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)
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(
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// Register clock
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input reg_clk,
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// Outputs to internal logic
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output b2r_t b2r,
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@ -46,8 +36,8 @@ module srdl2sv_amba3ahblite
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input r2b_t r2b,
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// Bus protocol
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input HRESETn,
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input HCLK,
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input HRESETn,
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input HSEL,
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input [31:0] HADDR,
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input HWRITE,
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@ -57,118 +47,240 @@ module srdl2sv_amba3ahblite
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input [ 1:0] HTRANS,
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input [31:0] HWDATA,
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input HREADY,
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input HMASTLOCK,
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output logic HREADYOUT,
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output logic HRESP,
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output logic [31:0] HRDATA
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);
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// TODO: Add synchronizer logic
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/***********************
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* Define enums
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***********************/
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typedef enum logic [2:0] {
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SINGLE = 3'b000,
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INCR = 3'b001,
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WRAP4 = 3'b010,
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INCR4 = 3'b011,
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WRAP8 = 3'b100,
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INCR8 = 3'b101,
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WRAP16 = 3'b110,
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INCR16 = 3'b111
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} HBURST_t;
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/***
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* Translate HWRITE & HSEL into a write/read operation for the register logic
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***/
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logic r_vld_next;
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logic w_vld_next;
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typedef enum logic [1:0] {
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IDLE = 2'b00,
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BUSY = 2'b01,
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NONSEQ = 2'b10,
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SEQ = 2'b11
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} HTRANS_t;
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typedef enum logic {
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OKAY = 1'b0,
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ERROR = 1'b1
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} HRESP_t;
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typedef enum logic {
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READ = 1'b0,
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WRITE = 1'b1
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} OP_t;
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typedef enum logic [2:0] {
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FSM_IDLE = 3'b000,
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FSM_NONSEQ= 3'b001,
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FSM_SEQ = 3'b010,
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FSM_WAIT = 3'b011,
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FSM_ERR_0 = 3'b100,
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FSM_ERR_1 = 3'b101
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} fsm_t;
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/****************************
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* Determine current address
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****************************/
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logic [31:0] addr_q;
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OP_t operation_q;
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wire addr_err = (HADDR % HSIZE) != 0;
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always_ff @ (posedge HCLK)
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begin
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case (HTRANS)
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IDLE: ;// Do nothing
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BUSY: ;// Do nothing
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NONSEQ:
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begin
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// When a transfer is extended it has the side-effecxt
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// of extending the address phase of the next transfer
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if (r2b.rdy)
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begin
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addr_q <= HADDR;
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operation_q <= HWRITE ? WRITE : READ;
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end
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end
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SEQ:
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begin
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if (r2b.rdy)
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begin
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addr_q <= addr_q; // TODO
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end
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end
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endcase
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end
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/****************************
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* Statemachine
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****************************/
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fsm_t fsm_next, fsm_q;
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always_comb
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begin
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w_vld_next = 1'b0;
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r_vld_next = 1'b0;
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// Defaults
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HREADYOUT = 1'b1;
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HRESP = 1'b0;
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HRDATA = r2b.data;
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if (HWRITE)
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w_vld_next = HSEL;
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else
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r_vld_next = HSEL;
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b2r_w_vld_next = 0;
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b2r_r_vld_next = 0;
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fsm_next = fsm_q;
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case (fsm_q)
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default: // FSM_IDLE
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begin
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if (HSEL && HTRANS > BUSY)
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begin
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if (addr_err)
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// In case the address is illegal, switch to an error state
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fsm_next = FSM_ERR_0;
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else if (HTRANS == NONSEQ)
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// If NONSEQ, go to NONSEQ state
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fsm_next = FSM_NONSEQ;
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else if (HTRANS == SEQ)
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// If a SEQ is provided, something is wrong
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fsm_next = FSM_ERR_0;
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end
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end
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FSM_NONSEQ:
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begin
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HREADYOUT = r2b.rdy;
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b2r_w_vld_next = operation_q == WRITE;
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b2r_r_vld_next = operation_q == READ;
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if (r2b.err && r2b.rdy)
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begin
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fsm_next = FSM_ERR_0;
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end
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else if (HTRANS == BUSY)
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begin
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// Wait
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fsm_next = FSM_NONSEQ;
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end
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else if (HTRANS == NONSEQ)
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begin
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// Another unrelated access is coming
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fsm_next = FSM_NONSEQ;
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end
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else if (HTRANS == SEQ)
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begin
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// Entering a burst
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fsm_next = r2b.rdy ? FSM_SEQ : FSM_NONSEQ;
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end
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else if (HTRANS == IDLE)
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begin
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// All done, wrapping things up!
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fsm_next = r2b.rdy ? FSM_IDLE : FSM_NONSEQ;
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end
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end
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FSM_SEQ:
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begin
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end
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FSM_WAIT:
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begin
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end
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FSM_ERR_0:
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begin
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HREADYOUT = 0;
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if (HTRANS == BUSY)
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begin
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// Slaves must always provide a zero wait state OKAY response
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// to BUSY transfers and the transfer must be ignored by the slave.
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HRESP = 0;
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fsm_next = FSM_ERR_0;
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end
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else
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begin
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HRESP = 1;
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fsm_next = FSM_ERR_1;
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end
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end
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FSM_ERR_1:
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begin
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HREADYOUT = 1;
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HRESP = 1;
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fsm_next = FSM_IDLE;
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end
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endcase
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end
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always_ff @ (posedge HCLK or negedge HRESETn)
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if (!HRESETn)
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fsm_q <= FSM_IDLE;
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else
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fsm_q <= fsm_next;
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/***
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* Determine the number of active bytes
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***/
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logic [3:0] b2r_byte_en_next;
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logic b2r_w_vld_next;
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logic b2r_r_vld_next;
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always_comb
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begin
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case (HTRANS)
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3'b000 : b2r_byte_en_next = 4'b0001;
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3'b001 : b2r_byte_en_next = 4'b0011;
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3'b010 : b2r_byte_en_next = 4'b1111;
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// TODO: Implement larger sizes
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default: b2r_byte_en_next = 4'b1111;
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endcase
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end
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//always_comb
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//begin
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// case (HTRANS)
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// 3'b000 : b2r_byte_en_next = 4'b0001;
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// 3'b001 : b2r_byte_en_next = 4'b0011;
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// 3'b010 : b2r_byte_en_next = 4'b1111;
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// default: b2r_byte_en_next = 4'b1111;
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// endcase
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//end
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/***
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* Flop or sync input if required
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* Drive interface to registers
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***/
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generate
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if (FLOP_IN)
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begin
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always_ff @(posedge HCLK or negedge HRESETn)
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if (FLOP_REGISTER_IF)
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begin
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always_ff @ (posedge HCLK or negedge HRESETn)
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if (!HRESETn)
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begin
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b2r.r_vld <= 1'b0;
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b2r.w_vld <= 1'b0;
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b2r.r_vld <= 1'b0;
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end
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else
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begin
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b2r.r_vld <= r_vld_next;
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b2r.w_vld <= w_vld_next;
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b2r.w_vld <= b2r_w_vld_next;
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b2r.r_vld <= b2r_r_vld_next;
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end
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always_ff @(posedge HCLK)
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if (HWRITE)
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begin
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b2r.data <= HWDATA;
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b2r.byte_en <= b2r_byte_en_next;
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end
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end
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else
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always_ff @ (posedge HCLK)
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begin
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assign b2r.r_vld = r_vld_next;
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assign b2r.w_vld = w_vld_next;
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assign b2r.data = HWDATA;
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b2r.addr <= addr_q;
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b2r.data <= HWDATA;
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b2r.byte_en <= b2r_byte_en_next;
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end
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end
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else
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begin
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assign b2r.w_vld = b2r_w_vld_next;
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assign b2r.r_vld = b2r_r_vld_next;
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assign b2r.addr = addr_q;
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assign b2r.data = HWDATA;
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assign b2r.byte_en = b2r_byte_en_next;
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end
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endgenerate
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/***
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* Keep track of an ungoing transaction
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***/
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logic reg_busy_q;
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always_ff @(posedge HCLK or negedge HRESETn)
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if (!HRESETn)
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reg_busy_q <= 1'b0;
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else if ((b2r.r_vld || b2r.w_vld) && !r2b.rdy)
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reg_busy_q <= 1'b1;
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else if (r2b.rdy)
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reg_busy_q <= 1'b0;
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assign HREADYOUT = !reg_busy_q;
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/***
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* Return to AHB bus once the register block is ready
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***/
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// Return actual data
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logic ongoing_read_q;
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always_ff @(posedge HCLK or negedge HRESETn)
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if (!HRESETn)
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ongoing_read_q <= 1'b0;
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else if (b2r.r_vld && !r2b.rdy)
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ongoing_read_q <= 1'b1;
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else if (r2b.rdy)
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ongoing_read_q <= 1'b0;
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always_ff @(posedge HCLK)
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if ((b2r.r_vld || ongoing_read_q) && r2b.rdy)
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HRDATA <= r2b.data;
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// Did an error occur while reading?
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always_ff @(posedge HCLK or negedge HRESETn)
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if (!HRESETn)
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HRESP <= 1'b0;
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else
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HRESP <= r2b.err;
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endmodule
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@ -9,18 +9,11 @@ module_instantiation:
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* - b2r.* -> Signals from bus to registers
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* - H* -> Signals as defined in AMBA3 AHB Lite
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* specification
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* - bus_clk -> Clock that that drives signals on bus
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* - reg_clk -> Clock that drives register flops
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* - bus_rst_n -> Asynchronous reset that resets only the bus (but
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* (not the registers). The deassertion of this
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* reset shall be synchronized to bus_clk
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* - clk -> Clock that drives registers and the bus
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*******************************************************************/
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srdl2sv_amba3ahblite
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srdl2sv_amba3ahblite_inst
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(// Register clock
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.reg_clk,
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// Outputs to internal logic
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(// Outputs to internal logic
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.b2r,
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// Inputs from internal logic
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@ -28,7 +21,7 @@ module_instantiation:
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// Bus protocol
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.HRESETn,
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.HCLK,
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.HCLK (clk),
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.HADDR,
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.HWRITE,
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.HSIZE,
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@ -38,6 +31,7 @@ module_instantiation:
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.HWDATA,
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.HREADY,
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.HSEL,
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.HMASTLOCK,
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.HREADYOUT,
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.HRESP,
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@ -48,9 +42,9 @@ module_instantiation:
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- name: 'r2b'
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signal_type: 'r2b_t'
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input_ports:
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- name: 'HRESETn'
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- name: 'clk'
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signal_type: ''
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- name: 'HCLK'
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- name: 'HRESETn'
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signal_type: ''
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- name: 'HADDR'
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signal_type: '[31:0]'
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@ -70,6 +64,8 @@ module_instantiation:
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signal_type: ''
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- name: 'HSEL'
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signal_type: ''
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- name: 'HMASTLOCK'
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signal_type: ''
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output_ports:
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- name: 'HREADYOUT'
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signal_type: ''
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