Improve counter property
The counter now covers more corner cases regarding saturation.
Furthermore, a bug that caused incr & decr-counters to always
inadvertently increment and decrement, even if only one of the two
signals was set.
Furthermore, the overflow signal is now generated in RTL.
Still missing:
- incrthreshold/decrthreshold is not yet supported
- It is not yet supported to assign an underflow/overflow to the
input of another counter.
This commit is contained in:
parent
4144329f3f
commit
18204d9a3e
GPG Key ID:
186A8AD440942BAF
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@ -212,22 +212,30 @@ class Field(Component):
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if self.obj.get_property('counter'):
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self.logger.debug("Detected counter property")
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# Determine saturation values
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self.rtl_footer.append(Field.templ_dict['counter_comment']['rtl'])
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# Determine saturation values and add appropriate RTL
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if isinstance(self.obj.get_property('incrsaturate'), bool):
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if self.obj.get_property('incrsaturate'):
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incr_sat_value = 2**self.obj.width-1
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overflow_value = incr_sat_value
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else:
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incr_sat_value = False
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overflow_value = 2**self.obj.width-1
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else:
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incr_sat_value = self.obj.get_property('incrsaturate')
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overflow_value = incr_sat_value
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if isinstance(self.obj.get_property('decrsaturate'), bool):
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if self.obj.get_property('decrsaturate'):
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decr_sat_value = 2**self.obj.width-1
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decr_sat_value = 0
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underflow_value = decr_sat_value
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else:
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decr_sat_value = False
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underflow_value = 0
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else:
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decr_sat_value = self.obj.get_property('decrsaturate')
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underflow_value = decr_sat_value
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# Determine with what value the counter is incremented
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# According to the spec, the incrvalue/decrvalue default to '1'
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@ -236,19 +244,23 @@ class Field(Component):
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obj_incr_width = self.obj.get_property('incrwidth')
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obj_decr_width = self.obj.get_property('decrwidth')
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incr_width_input = False
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if obj_incr_value == 0:
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incr_value = None
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incr_width = 0
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incr_value = 0
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incr_width = 1
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elif obj_incr_value is None:
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# Increment value is not set. Check if incrwidth is set and use
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# that is applicable
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if obj_incr_width:
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# Decrement value is not set. Check if incrwidth is set and use
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# that is applicable
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incr_value = False
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incr_width = obj_incr_width
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incr_width_input = True
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# Doesn't return RTL, only adds input port
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self.process_yaml(
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Field.templ_dict['counter_incr_input'],
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Field.templ_dict['counter_incr_val_input'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width-1
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@ -259,6 +271,7 @@ class Field(Component):
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incr_value = '1'
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incr_width = 1
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elif isinstance(obj_incr_value, int):
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# An explicit width is set for the incr_val
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incr_value = str(obj_incr_value)
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incr_width = math.floor(math.log2(obj_incr_value)+1)
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@ -284,10 +297,12 @@ class Field(Component):
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"will be ignored!")
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if incr_value:
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# If no input is defined for the increment value, define
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# an internal signal. It is possible that this is tied to 0.
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if not incr_width_input:
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_internal_incr_signal'],
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Field.templ_dict['counter_internal_incr_val_signal'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width-1,
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@ -296,19 +311,24 @@ class Field(Component):
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)
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)
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# Handle decrement value
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decr_width_input = False
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if obj_decr_value == 0:
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decr_value = None
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decr_width = 0
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elif obj_decr_value is None:
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decr_value = 0
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decr_width = 1
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elif obj_incr_value is None:
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# Decrement value is not set. Check if decrwidth is set and use
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# that is applicable
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if obj_decr_width:
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# Decrement value is not set. Check if decrwidth is set and use
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# that is applicable
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decr_value = False
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decr_width = obj_decr_width
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decr_width_input = True
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# Doesn't return RTL, only adds input port
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self.process_yaml(
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Field.templ_dict['counter_decr_input'],
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Field.templ_dict['counter_decr_val_input'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'decr_width': decr_width-1
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@ -319,6 +339,7 @@ class Field(Component):
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decr_value = '1'
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decr_width = 1
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elif isinstance(obj_decr_value, int):
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# An explicit width is set for the decr_val
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decr_value = str(obj_decr_value)
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decr_width = math.floor(math.log2(obj_decr_value)+1)
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@ -344,10 +365,12 @@ class Field(Component):
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"will be ignored!")
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if decr_value:
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# If no input is defined for the decrement value, define
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# an internal signal. It is possible that this is tied to 0.
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if not decr_width_input:
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_internal_decr_signal'],
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Field.templ_dict['counter_internal_decr_val_signal'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'decr_width': decr_width-1,
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@ -356,92 +379,174 @@ class Field(Component):
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)
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)
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if (incr_width or incr_value) and (decr_width or decr_value):
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sat_condition = []
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if incr_sat_value:
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sat_condition.append(
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self.process_yaml(
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Field.templ_dict['incr_decr_sat_counter_condition'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'greater_smaller': '>',
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'sat_value': incr_sat_value
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}
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)
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)
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if decr_sat_value:
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if sat_condition:
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sat_condition.append(' && ')
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sat_condition.append(
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self.process_yaml(
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Field.templ_dict['incr_decr_sat_counter_condition'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'greater_smaller': '<',
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'sat_value': decr_sat_value
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}
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)
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)
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counter_logic = self.process_yaml(
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Field.templ_dict['incr_decr_counter'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_decr_sat_counter_condition': ''.join(sat_condition),
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}
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)
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elif incr_width or incr_value:
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sat_condition = self.process_yaml(
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Field.templ_dict['incr_sat_counter_condition'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'sat_value': incr_sat_value,
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}
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) if incr_sat_value else '1'
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counter_logic = self.process_yaml(
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Field.templ_dict['incr_counter'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_sat_counter_condition': sat_condition,
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}
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)
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elif decr_width or decr_value:
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sat_condition = self.process_yaml(
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Field.templ_dict['decr_sat_counter_condition'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'sat_value': decr_sat_value,
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}
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) if decr_sat_value else '1'
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counter_logic = self.process_yaml(
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Field.templ_dict['decr_counter'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'decr_sat_counter_condition': sat_condition,
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}
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)
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else:
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# Handle the increment/decrement signals.
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# If the increment or decrement signal is not set, use an input
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# if the decrement value is bigger than 0
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if not incr_value and not decr_value:
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self.logger.fatal("Illegal counter configuration! Both 'incr_value' "\
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"and 'decr_value' are forced to 0. If you intended "\
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"to use 'incr_width' or 'decr_width', simply don't "\
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"force 'incr_value' or 'decr_value' to any value.")
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sys.exit(1)
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if incr_value:
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incr = self.obj.get_property('incr')
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if not incr:
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# Will only add input port but not return any RTL
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self.process_yaml(
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Field.templ_dict['counter_incr_input'],
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{'path': self.path_underscored}
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)
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else:
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_internal_incr_signal'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr': self.get_signal_name(incr)
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}
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)
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)
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if incr.width > 0:
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self.logger.error("Increment signal '{}' is wider than 1-bit. "\
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"This might result in unwanted behavior and "\
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"will also cause Lint-errors.".format(
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incr.inst_name))
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else:
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# Tie signal to 0
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_internal_incr_signal'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr': '0'
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}
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)
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)
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if decr_value:
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decr = self.obj.get_property('decr')
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if not self.obj.get_property('decr'):
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# Will only add input port but not return any RTL
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self.process_yaml(
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Field.templ_dict['counter_decr_input'],
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{'path': self.path_underscored}
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)
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else:
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_internal_decr_signal'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'decr': self.get_signal_name(decr)
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}
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)
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)
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if decr.width > 0:
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self.logger.error("Decrement signal '{}' is wider than 1-bit. "\
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"This might result in unwanted behavior and "\
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"will also cause Lint-errors.".format(
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decr.inst_name))
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else:
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# Tie signal to 0
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_internal_decr_signal'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'decr': '0'
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}
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)
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)
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# Handle saturation signals
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if not incr_sat_value:
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_incr_sat_tied'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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}
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)
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)
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else:
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_incr_sat'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width,
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'decr_width': decr_width,
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'sat_value': incr_sat_value,
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}
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)
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)
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if not decr_sat_value:
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_decr_sat_tied'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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}
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)
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)
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else:
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_decr_sat'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width,
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'decr_width': decr_width,
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'sat_value': decr_sat_value,
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}
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)
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)
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# Handle overflow & underflow signals
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if self.obj.get_property('overflow'):
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_overflow'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width,
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'decr_width': decr_width,
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'overflow_value': overflow_value,
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}
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)
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)
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if self.obj.get_property('underflow'):
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_underflow'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width,
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'decr_width': decr_width,
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'underflow_value': underflow_value,
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}
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)
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)
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# Implement actual counter logic
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'counter_logic': counter_logic,
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'field_type': self.field_type,
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}
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)
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)
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def __add_swmod_swacc(self):
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if self.obj.get_property('swmod'):
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self.logger.debug("Field has swmod property")
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@ -92,7 +92,7 @@ hw_access_field:
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signal_type: '{field_type}'
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hw_access_counter:
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rtl: |-
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if ({path}_update_cnt{genvars})
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if ({path}_incr{genvars} || {path}_decr{genvars})
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<<INDENT>>
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{enable_mask_start}
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{path}_q{genvars}{idx} <= {path}_next{genvars}{idx};
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@ -226,93 +226,145 @@ swmod_assign:
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output_ports:
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- name: '{path}_swmod'
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signal_type: 'logic'
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counter_comment:
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rtl: |-
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/***********************
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* Counter Combo Logic *
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***********************/
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counter:
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rtl: |-
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// Combinational logic that implements counter
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// Note that the three branches for all three possibilities
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// are implemented but that either the _incr or the _decr value
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// might be tied to 0.
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always_comb
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begin
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{path}_next{genvars} = {path}_q{genvars};
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{path}_update_cnt{genvars} = 0;
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{counter_logic}
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{path}_next{genvars} = {path}_q{genvars};
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if ({path}_incr{genvars} && {path}_decr{genvars})
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begin
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if (!{path}_incr_sat{genvars} && !{path}_decr_sat{genvars})
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begin
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{path}_next{genvars} += {path}_incr_val{genvars};
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{path}_next{genvars} -= {path}_decr_val{genvars};
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end
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end
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else if ({path}_incr{genvars})
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begin
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if (!{path}_incr_sat{genvars})
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<<INDENT>>
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{path}_next{genvars} += {path}_incr_val{genvars};
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<<UNINDENT>>
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end
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else if ({path}_decr{genvars})
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begin
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if (!{path}_decr_sat{genvars})
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<<INDENT>>
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{path}_next{genvars} += {path}_decr_val{genvars};
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<<UNINDENT>>
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end
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end
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signals:
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- name: '{path}_update_cnt'
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signal_type: 'logic'
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- name: '{path}_next'
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signal_type: '{field_type}'
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counter_internal_incr_signal:
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counter_internal_incr_val_signal:
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rtl: |-
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assign {path}_incr_val{genvars} = {incr_value};
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signals:
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- name: '{path}_incr_val'
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signal_type: 'logic [{incr_width}:0]'
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counter_internal_decr_signal:
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counter_internal_decr_val_signal:
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rtl: |-
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assign {path}_decr_val{genvars} = {decr_value};
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signals:
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- name: '{path}_decr_val'
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signal_type: 'logic [{decr_width}:0]'
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counter_incr_input:
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counter_incr_val_input:
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rtl: ''
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input_ports:
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- name: '{path}_incr_val'
|
||||
signal_type: 'logic [{incr_width}:0]'
|
||||
counter_decr_input:
|
||||
counter_decr_val_input:
|
||||
rtl: ''
|
||||
input_ports:
|
||||
- name: '{path}_decr_val'
|
||||
signal_type: 'logic [{decr_width}:0]'
|
||||
incr_counter:
|
||||
counter_internal_incr_signal:
|
||||
rtl: |-
|
||||
if ({path}_incr{genvars})
|
||||
begin
|
||||
if ({incr_sat_counter_condition})
|
||||
begin
|
||||
{path}_next{genvars} += {path}_incr_val{genvars};
|
||||
{path}_update_cnt{genvars} = 1;
|
||||
end
|
||||
end
|
||||
input_ports:
|
||||
assign {path}_incr{genvars} = {incr};
|
||||
signals:
|
||||
- name: '{path}_incr'
|
||||
signal_type: 'logic'
|
||||
decr_counter:
|
||||
counter_internal_decr_signal:
|
||||
rtl: |-
|
||||
if ({path}_decr{genvars})
|
||||
begin
|
||||
if ({decr_sat_counter_condition})
|
||||
begin
|
||||
{path}_next{genvars} -= {path}_decr_val{genvars};
|
||||
{path}_update_cnt{genvars} = 1;
|
||||
end
|
||||
end
|
||||
input_ports:
|
||||
assign {path}_decr{genvars} = {decr};
|
||||
signals:
|
||||
- name: '{path}_decr'
|
||||
signal_type: 'logic'
|
||||
incr_decr_counter:
|
||||
rtl: |-
|
||||
if ({path}_incr{genvars} || {path}_decr{genvars})
|
||||
begin
|
||||
if ({incr_decr_sat_counter_condition})
|
||||
begin
|
||||
{path}_next{genvars} += {path}_incr_val{genvars};
|
||||
{path}_next{genvars} -= {path}_decr_val{genvars};
|
||||
{path}_update_cnt{genvars} = 1;
|
||||
end
|
||||
end
|
||||
counter_incr_input:
|
||||
rtl: ''
|
||||
input_ports:
|
||||
- name: '{path}_incr'
|
||||
signal_type: 'logic'
|
||||
signal_type: ''
|
||||
counter_decr_input:
|
||||
rtl: ''
|
||||
input_ports:
|
||||
- name: '{path}_decr'
|
||||
signal_type: ''
|
||||
counter_incr_sat:
|
||||
rtl: |-
|
||||
|
||||
// Determine whether the counter is saturated
|
||||
// The signal is tied if the counter is not saturating
|
||||
// in the respective direction
|
||||
assign {path}_incr_sat{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {sat_value};
|
||||
signals:
|
||||
- name: '{path}_incr_sat'
|
||||
signal_type: 'logic'
|
||||
incr_sat_counter_condition:
|
||||
counter_incr_sat_tied:
|
||||
rtl: |-
|
||||
{path}_next{genvars} + {path}_incr_val{genvars} <= {sat_value}
|
||||
decr_sat_counter_condition:
|
||||
|
||||
// Determine whether the counter is saturated
|
||||
// The signal is tied if the counter is not saturating
|
||||
// in the respective direction
|
||||
assign {path}_incr_sat{genvars} = 1'b0;
|
||||
signals:
|
||||
- name: '{path}_incr_sat'
|
||||
signal_type: 'logic'
|
||||
counter_decr_sat:
|
||||
rtl: |-
|
||||
{path}_next{genvars} - {path}_decr_val{genvars} >= {sat_value}
|
||||
incr_decr_sat_counter_condition:
|
||||
assign {path}_decr_sat{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {sat_value};
|
||||
signals:
|
||||
- name: '{path}_decr_sat'
|
||||
signal_type: 'logic'
|
||||
counter_decr_sat_tied:
|
||||
rtl: |-
|
||||
({path}_next{genvars} + {path}_incr_val{genvars} - {path}_decr_val{genvars} {greater_smaller}= {sat_value})
|
||||
assign {path}_decr_sat{genvars} = 1'b0;
|
||||
signals:
|
||||
- name: '{path}_decr_sat'
|
||||
signal_type: 'logic'
|
||||
counter_overflow:
|
||||
rtl: |-
|
||||
|
||||
// Logic to determine occurance of an overflow
|
||||
assign {path}_overflow_int{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {overflow_value};
|
||||
assign {path}_overflow{genvars} = {path}_incr{genvars} && {path}_overflow_int{genvars};
|
||||
signals:
|
||||
- name: '{path}_overflow_int'
|
||||
signal_type: 'logic'
|
||||
output_ports:
|
||||
- name: '{path}_overflow'
|
||||
signal_type: 'logic'
|
||||
counter_underflow:
|
||||
rtl: |-
|
||||
|
||||
// Logic to determine occurance of an underflow
|
||||
assign {path}_underflow_int{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {underflow_value};
|
||||
assign {path}_underflow{genvars} = {path}_incr{genvars} && {path}_underflow_int{genvars};
|
||||
signals:
|
||||
- name: '{path}_underflow_int'
|
||||
signal_type: 'logic'
|
||||
output_ports:
|
||||
- name: '{path}_underflow'
|
||||
signal_type: 'logic'
|
||||
|
|
|
|||
Loading…
Reference in New Issue