Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-11-14 03:03:35 +00:00
Code Issues Projects Releases Wiki Activity

Resolve bug for addrmaps without any genvars

Browse Source 
In this case, there would be a line with `genvars ;`. This is not
compilable by SystemVerilog compilers.
This commit is contained in:
Dennis Potter 2021-09-12 19:37:30 -07:00
parent 17f1877390
commit 240fba8e12
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
1 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
srdl2sv/components/addrmap.py
View File

@ -264,13 +264,16 @@ class AddrMap(Component):
def __append_genvars(self): def __append_genvars(self):
genvars = ''.join([ genvars = ', '.join([chr(97+i) for i in range(self.get_max_dim_depth())])
'\ngenvar ',
', '.join([chr(97+i) for i in range(self.get_max_dim_depth())]),
';\n'
])
self.rtl_header.append(genvars) if genvars:
genvars_instantiation = ''.join([
'\ngenvar ',
genvars,
';\n'
])
self.rtl_header.append(genvars_instantiation)
def get_package_names(self) -> set(): def get_package_names(self) -> set():
names = set() names = set()