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Pull assignment of multiplexer wires into generate for-loop

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This commit is contained in:
Dennis Potter 2021-09-19 23:24:59 -07:00
parent 887164dd52
commit 28edf17a1c
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
1 changed files with 4 additions and 4 deletions
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8
srdl2sv/components/register.py
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@ -68,6 +68,9 @@ class Register(Component):
# Fields will be added by get_rtl()
# Add assignment of read-wires
self.__add_sw_mux_assignments()
# Add N layers of for-loop end
for i in range(self.dimensions-1, -1, -1):
self.rtl_footer.append(
@ -75,10 +78,7 @@ class Register(Component):
dimension = chr(97+i)))
if self.dimensions and not self.generate_active:
self.rtl_footer.append("endgenerate\n")
# Add assignment of read-wires
self.__add_sw_mux_assignments()
self.rtl_footer.append("\nendgenerate\n")
# Add wire instantiation
if not self.generate_active: