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https://github.com/Silicon1602/srdl2sv.git
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Add swmod and swacc properties and fix field-range bug
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parent
95fef548cf
commit
2e22d82146
@ -1,4 +1,5 @@
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import math
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import importlib.resources as pkg_resources
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import yaml
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@ -47,6 +48,7 @@ class Field(Component):
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self.__add_combo()
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self.add_sw_access(obj)
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self.add_swmod_swacc(obj)
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def add_sw_access(self, obj, alias = False):
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access_rtl = dict()
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@ -117,6 +119,9 @@ class Field(Component):
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else:
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# If field spans multiple bytes, every byte shall have a seperate enable!
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for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
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msb_bus = 8*(i+1)-1 if i != self.msbyte else obj.msb
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lsb_bus = 8*i if i != self.lsbyte else obj.inst.lsb
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access_rtl['sw_write'][0].append(
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self.process_yaml(
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Field.templ_dict[str(onwrite)],
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@ -124,10 +129,10 @@ class Field(Component):
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'genvars': self.genvars_str,
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'i': i,
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'width': obj.width,
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'msb_bus': str(8*(i+1)-1 if i != self.msbyte else obj.msb),
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'bus_w': str(8 if i != self.msbyte else obj.width-(8*j)),
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'msb_field': str(8*(j+1)-1 if i != self.msbyte else obj.width-1),
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'field_w': str(8 if i != self.msbyte else obj.width-(8*j)),
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'msb_bus': str(msb_bus),
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'lsb_bus': str(lsb_bus),
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'msb_field': str(msb_bus-obj.inst.lsb),
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'lsb_field': str(lsb_bus-obj.inst.lsb),
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'field_type': self.field_type}
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)
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)
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@ -136,16 +141,19 @@ class Field(Component):
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# Normal write
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# If field spans multiple bytes, every byte shall have a seperate enable!
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for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
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msb_bus = 8*(i+1)-1 if i != self.msbyte else obj.msb
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lsb_bus = 8*i if i != self.lsbyte else obj.inst.lsb
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access_rtl['sw_write'][0].append(
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self.process_yaml(
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Field.templ_dict['sw_access_byte'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'i': i,
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'msb_bus': str(8*(i+1)-1 if i != self.msbyte else obj.msb),
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'bus_w': str(8 if i != self.msbyte else obj.width-(8*j)),
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'msb_field': str(8*(j+1)-1 if i != self.msbyte else obj.width-1),
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'field_w': str(8 if i != self.msbyte else obj.width-(8*j)),
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'msb_bus': str(msb_bus),
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'lsb_bus': str(lsb_bus),
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'msb_field': str(msb_bus-obj.inst.lsb),
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'lsb_field': str(lsb_bus-obj.inst.lsb),
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'field_type': self.field_type}
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)
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)
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@ -198,6 +206,68 @@ class Field(Component):
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self.access_rtl['sw_read'] = [access_rtl['sw_read']]
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self.access_rtl['sw_write'] = [access_rtl['sw_write']]
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def add_swmod_swacc(self, obj):
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if obj.get_property('swmod'):
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swmod_assigns = list()
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swacc_assigns = list()
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# Check if read side-effects are defined.
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if obj.get_property('onread'):
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swmod_assigns.append(
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self.process_yaml(
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Field.templ_dict['swmod_assign'],
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{'path': self.path_underscored,
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'path_wo_field': self.path_wo_field,
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'genvars': self.genvars_str,
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'rd_wr': 'rd',
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'msbyte': self.msbyte,
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'lsbyte': self.lsbyte,
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'swmod_assigns': '\n'.join(swmod_assigns)
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}
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)
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)
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# Check if SW has write access to the field
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if obj.get_property('sw') in (AccessType.rw, AccessType.w):
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swmod_assigns.append(
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self.process_yaml(
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Field.templ_dict['swmod_assign'],
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{'path': self.path_underscored,
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'path_wo_field': self.path_wo_field,
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'genvars': self.genvars_str,
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'rd_wr': 'wr',
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'msbyte': self.msbyte,
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'lsbyte': self.lsbyte,
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'swmod_assigns': '\n'.join(swmod_assigns)
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}
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)
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)
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swmod_props = self.process_yaml(
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Field.templ_dict['swmod_always_comb'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'swmod_assigns': '\n'.join(swmod_assigns)
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}
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)
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else:
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swmod_props = ''
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if obj.get_property('swacc') and obj.get_property('sw') in (AccessType.rw, AccessType.r):
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swacc_props = self.process_yaml(
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Field.templ_dict['swacc_assign'],
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{'path': self.path_underscored,
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'path_wo_field': self.path_wo_field,
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'genvars': self.genvars_str,
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'msbyte': self.msbyte,
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'lsbyte': self.lsbyte,
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}
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)
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else:
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swacc_props = ''
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self.rtl_footer = [*self.rtl_footer, swmod_props, swacc_props]
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def __add_hw_access(self):
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# Define hardware access (if applicable)
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if self.obj.get_property('hw') in (AccessType.rw, AccessType.w):
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@ -182,6 +182,22 @@ class Register(Component):
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)
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) for i, x in enumerate(self.name_addr_mappings)]
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# Add combined signal to be used for general access of the register
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self.rtl_header.append(
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self.process_yaml(
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Register.templ_dict['rw_wire_assign_any_alias'],
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{'path': self.name_addr_mappings[0][0],
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'genvars': self.genvars_str,
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'sw_rds_w_genvars': ' || '.join(
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[''.join([x[0], '_sw_rd', self.genvars_str])
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for x in self.name_addr_mappings]),
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'sw_wrs_w_genvars': ' || '.join(
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[''.join([x[0], '_sw_wr', self.genvars_str])
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for x in self.name_addr_mappings])
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}
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)
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)
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def __add_signal_instantiations(self):
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# Add wire/register instantiations
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self.rtl_header = [
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@ -73,9 +73,6 @@ module_declaration:
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input bus_rst_n,
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{resets}
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// Bus I/O
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// TODO
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// Inputs
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{inputs}
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@ -31,7 +31,7 @@ sw_access_byte:
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rtl: |-
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if (byte_enable[{i}])
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= sw_wr_bus[{msb_bus}-:{bus_w}];
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{path}_q{genvars}[{msb_field}:{lsb_field}] <= sw_wr_bus[{msb_bus}:{lsb_bus}];
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end
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signals:
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- name: '{path}_q'
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@ -63,31 +63,31 @@ OnWriteType.woset:
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rtl: |-
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if (byte_enable[{i}]) // woset property
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] | sw_wr_bus[{msb_bus}-:{bus_w}];
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{path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] | sw_wr_bus[{msb_bus}:{lsb_bus}];
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end
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OnWriteType.woclr:
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rtl: |-
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if (byte_enable[{i}]) // woclr property
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] & ~sw_wr_bus[{msb_bus}-:{bus_w}];
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{path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] & ~sw_wr_bus[{msb_bus}:{lsb_bus}];
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end
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OnWriteType.wot:
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rtl: |-
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if (byte_enable[{i}]) // wot property
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] ^ sw_wr_bus[{msb_bus}-:{bus_w}];
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{path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] ^ sw_wr_bus[{msb_bus}:{lsb_bus}];
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end
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OnWriteType.wzs:
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rtl: |-
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if (byte_enable[{i}]) // wzs property
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] & sw_wr_bus[{msb_bus}-:{bus_w}];
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{path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] & sw_wr_bus[{msb_bus}:{lsb_bus}];
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end
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OnWriteType.wzt:
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rtl: |-
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if (byte_enable[{i}]) // wzt property
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] ~^ sw_wr_bus[{msb_bus}-:{bus_w}];
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{path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] ~^ sw_wr_bus[{msb_bus}:{lsb_bus}];
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end
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OnWriteType.wclr:
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rtl: |-
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@ -153,6 +153,32 @@ out_port_assign:
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output_ports:
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- name: '{path}_r'
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signal_type: '{field_type}'
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swacc_assign:
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rtl: |-
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// Combinational block to generate swacc-output signals
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assign {path}_swacc{genvars} = ({path_wo_field}__any_alias_sw_wr{genvars} || {path_wo_field}__any_alias_sw_rd{genvars}) && |byte_enable[{msbyte}:{lsbyte}];
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output_ports:
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- name: '{path}_swacc'
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signal_type: 'logic'
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swmod_always_comb:
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rtl: |-
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// Combinational block to generate swmod-output signals
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always_comb
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begin
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{path}_swmod{genvars} = 0;
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{swmod_assigns}
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end
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output_ports:
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- name: '{path}_swmod'
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signal_type: 'logic'
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swmod_assign:
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rtl: |-
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{path}_swmod{genvars} |= {path_wo_field}__any_alias_sw_{rd_wr}{genvars} && |byte_enable[{msbyte}:{lsbyte}];
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output_ports:
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- name: '{path}_swmod'
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signal_type: 'logic'
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counter:
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rtl: |-
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always_comb
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@ -190,9 +216,3 @@ decr_counter_condition:
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decr_sat_counter_condition:
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rtl: |-
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if ({path}_decr{genvars} && {path}_next{genvars} - {path}_decr_val{genvars} >= {sat_value})
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@ -1,6 +1,7 @@
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---
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rw_wire_assign_1_dim:
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rtl: |
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// Register-activation for '{path}' {alias}
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assign {path}_accss = addr == {addr};
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assign {path}_sw_wr = {path}_accss && r_vld;
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@ -12,10 +13,9 @@ rw_wire_assign_1_dim:
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signal_type: 'logic'
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- name: '{path}_accss'
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signal_type: 'logic'
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input_ports:
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output_ports:
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rw_wire_assign_multi_dim:
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rtl: |-
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// Register-activation for '{path}' {alias}
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assign {path}_accss{genvars} = addr == {addr}+({genvars_sum});
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assign {path}_sw_wr{genvars} = {path}_accss{genvars} && r_vld;
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@ -27,8 +27,18 @@ rw_wire_assign_multi_dim:
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signal_type: 'logic'
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- name: '{path}_accss'
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signal_type: 'logic'
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input_ports:
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output_ports:
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rw_wire_assign_any_alias:
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rtl: |-
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// Combined register activation. These will become active
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// _any_ alias accesses a certain register.
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assign {path}__any_alias_sw_wr{genvars} = {sw_wrs_w_genvars};
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assign {path}__any_alias_sw_rd{genvars} = {sw_rds_w_genvars};
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signals:
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- name: '{path}__any_alias_sw_wr'
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signal_type: 'logic'
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- name: '{path}__any_alias_sw_rd'
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signal_type: 'logic'
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reg_comment: |-
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/*******************************************************************
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