Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-12-22 06:58:41 +00:00
Code Issues Projects Releases Wiki Activity

Closes #9: Error returns from regblock now actually get processed by AHB widget

Browse Source
This commit is contained in:
Dennis Potter 2021-10-30 23:30:55 -07:00
parent 031e413d17
commit 33c92c8994
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
1 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv
View File

@ -135,7 +135,7 @@ module srdl2sv_amba3ahblite #(
begin
// Defaults
HREADYOUT = 1'b1;
HRESP = 1'b0;
HRESP = OKAY;
// When reading back, the data of the bit that was accessed over the bus
// should be at byte 0 of the HRDATA bus and bits that were not accessed
@ -174,15 +174,17 @@ module srdl2sv_amba3ahblite #(
widget_if_w_vld_next = operation_q == WRITE;
widget_if_r_vld_next = operation_q == READ;
if (widget_if.err && widget_if.rdy)
begin
fsm_next = FSM_ERR_0;
end
else if (HTRANS == BUSY)
if (HTRANS == BUSY)
begin
// Wait
fsm_next = FSM_TRANS;
end
else if (widget_if.err && widget_if.rdy)
begin
HREADYOUT = 0;
HRESP = ERROR;
fsm_next = FSM_ERR_1;
end
else if (HTRANS == NONSEQ)
begin
// Another unrelated access is coming
@ -306,3 +308,4 @@ module srdl2sv_amba3ahblite #(
endgenerate
endmodule