Add support for 1 packed and 26 unpacked dimensions in addrmap's I/O

srdl2sv/components/addrmap.py

@@ -59,18 +59,20 @@ class AddrMap(Component):
         # Start assembling addrmap module
         self.logger.info("Starting to assemble input/output/inout ports")
 
-        # Inout port
-        inout_ports_rtl = [
-            AddrMap.templ_dict['inout_port'].format(
-                name = x) for x in self.get_ports('inout')]
         # Input ports
         input_ports_rtl = [
             AddrMap.templ_dict['input_port'].format(
-                name = x) for x in self.get_ports('input')]
+                name = x.name,
+                packed_dim = x.packed_dim,
+                unpacked_dim = '[{}]'.format(']['.join([str(y) for y in x.unpacked_dim])))
+            for x in self.get_ports('input')]
         # Output ports
         output_ports_rtl = [
             AddrMap.templ_dict['output_port'].format(
-                name = x) for x in self.get_ports('output')]
+                name = x.name,
+                packed_dim = x.packed_dim,
+                unpacked_dim = '[{}]'.format(']['.join([str(y) for y in x.unpacked_dim])))
+            for x in self.get_ports('output')]
 
         # Remove comma from last port entry
         output_ports_rtl[-1] = output_ports_rtl[-1].rstrip(',')
@@ -78,14 +80,9 @@ class AddrMap(Component):
         self.rtl_header.append(
             AddrMap.templ_dict['module_declaration'].format(
                 name = obj.inst_name,
-                inouts = '\n'.join(inout_ports_rtl),
                 inputs = '\n'.join(input_ports_rtl),
                 outputs = '\n'.join(output_ports_rtl)))
 
-
-
-
-
     def __process_variables(self, obj: node.RootNode):
         # Save object
         self.obj = obj

srdl2sv/components/component.py

@@ -1,9 +1,16 @@
 import re
 from itertools import chain
+from typing import NamedTuple
 
 # Local modules
 from log.log import create_logger
 
+# Define NamedTuple
+class Port(NamedTuple):
+    name: str
+    packed_dim: str
+    unpacked_dim: list
+
 class Component():
     def __init__(self):
         self.rtl_header = []

srdl2sv/components/field.py

@@ -8,7 +8,7 @@ from systemrdl.rdltypes import PrecedenceType, AccessType
 
 # Local modules
 from log.log import create_logger
-from components.component import Component
+from components.component import Component, Port
 from . import templates
 
 class Field(Component):
@@ -17,7 +17,7 @@ class Field(Component):
         pkg_resources.read_text(templates, 'fields.yaml'),
         Loader=yaml.FullLoader)
 
-    def __init__(self, obj: node.RootNode, dimensions: int, config:dict):
+    def __init__(self, obj: node.RootNode, dimensions: list, config:dict):
         super().__init__()
 
         # Save and/or process important variables
@@ -181,7 +181,7 @@ class Field(Component):
             ]
 
 
-    def __process_variables(self, obj: node.RootNode, dimensions: int):
+    def __process_variables(self, obj: node.RootNode, dimensions: list):
         # Save object
         self.obj = obj
 
@@ -194,8 +194,11 @@ class Field(Component):
         self.path_underscored = self.path.replace('.', '_')
         self.path_wo_field = '.'.join(self.path.split('.', -1)[0:-1])
 
+        # Save dimensions of unpacked dimension
+        self.dimensions = dimensions
+
         # Calculate how many genvars shall be added
-        genvars = ['[{}]'.format(chr(97+i)) for i in range(dimensions)]
+        genvars = ['[{}]'.format(chr(97+i)) for i in range(len(dimensions))]
         self.genvars_str = ''.join(genvars)
 
         # Write enable
@@ -267,14 +270,26 @@ class Field(Component):
     def __add_ports(self):
         # Port is writable by hardware --> Input port from hardware
         if self.hw_access in (AccessType.rw, AccessType.w):
-            self.ports['input'].append("{}_in".format(self.path_underscored))
+            self.ports['input'].append(
+                Port("{}_in".format(self.path_underscored),
+                     "",
+                     self.dimensions
+                ))
 
             # Port has enable signal --> create such an enable
             if self.we_or_wel:
-                self.ports['input'].append("{}_hw_wr".format(self.path_underscored))
+                self.ports['input'].append(
+                    Port("{}_hw_wr".format(self.path_underscored),
+                         "",
+                         self.dimensions
+                    ))
 
         if self.hw_access in (AccessType.rw, AccessType.r):
-            self.ports['output'].append("{}_r".format(self.path_underscored))
+            self.ports['output'].append(
+                Port("{}_r".format(self.path_underscored),
+                     "[{}-1:0]".format(self.obj.width) if self.obj.width > 0 else "",
+                     self.dimensions
+                ))
 
     def sanity_checks(self):
         # If hw=rw/sw=[r]w and hw has no we/wel, sw will never be able to write

srdl2sv/components/register.py

@@ -61,7 +61,7 @@ class Register(Component):
         # Create RTL for fields
         # Fields should be in order in RTL,therefore, use list
         for field in obj.fields():
-            field_obj = Field(field, dimensions, config)
+            field_obj = Field(field, array_dimensions, config)
 
             if not config['disable_sanity']:
                 field_obj.sanity_checks()

srdl2sv/components/templates/addrmap.yaml

@@ -4,9 +4,6 @@ module_declaration: |-
     // Bus I/O
     // TODO
 
-    // InOuts
-    {inouts}
-
     // Inputs
     {inputs}
 
@@ -14,8 +11,6 @@ module_declaration: |-
     {outputs}
     );
 input_port: |-
-    input       {name},
+    input  {packed_dim:10s}{name:30s} {unpacked_dim},
 output_port: |-
-    output      {name},
+    output {packed_dim:10s}{name:30s} {unpacked_dim},
-inout_port: |-
-    inout       {name},