Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-09-21 08:40:25 +00:00
Code Issues Projects Releases Wiki Activity
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
8 Commits 1 Branch 0 Tags 713 KiB
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%
4738cbfe6c
Go to file
Dennis 4738cbfe6c
Add support for 1 packed and 26 unpacked dimensions in addrmap's I/O
2021-05-15 01:17:06 +02:00
srdl2sv Add support for 1 packed and 26 unpacked dimensions in addrmap's I/O 2021-05-15 01:17:06 +02:00
.gitignore Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00
LIMITATIONS.md Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00