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Dennis
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srdl2sv
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Dennis
4738cbfe6c
Add support for 1 packed and 26 unpacked dimensions in addrmap's I/O
2021-05-15 01:17:06 +02:00
srdl2sv
Add support for 1 packed and 26 unpacked dimensions in addrmap's I/O
2021-05-15 01:17:06 +02:00
.gitignore
Initial commit of SRDL2SV
2021-05-02 00:58:43 +02:00
LIMITATIONS.md
Initial commit of SRDL2SV
2021-05-02 00:58:43 +02:00
Description
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
asic
fpga
hardware-description-language
hdl
rdl
register-description-language
registers
systemrdl
systemrdl-compiler
systemverilog
verilog
713
KiB
Languages
Python
92.9%
SystemVerilog
5.7%
Makefile
1.4%
