Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2025-08-23 16:53:05 +00:00
Code Issues Projects Releases Wiki Activity
8 Commits 1 Branch 0 Tags
4738cbfe6c560b6db807940e5cb4182b4b3cc281
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Description
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
asicfpgahardware-description-languagehdlrdlregister-description-languageregisterssystemrdlsystemrdl-compilersystemverilogverilog
GPL-3.0 713 KiB
Languages
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%