Extend test_simple_rw_reg with 3 more tests
The following tests are now included:
- Check access to registers over AHB bus
- Check access to register over HW interface
- Check access to register over HW interface if hw_wr-input
is disabled.
- Check if the slave responds with a correct error sequence if
an illegal address is accessed.
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GPG Key ID:
186A8AD440942BAF
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@ -3,8 +3,14 @@ import math
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import cocotb
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from cocotb.triggers import Timer, RisingEdge
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# TODO: Does not yet implement HREADY_OUT == 0
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# TODO: Add support for HRESP (and throw error if HRESP occurs)
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class BusErrorResponse(Exception):
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pass
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class WrongErrorSequence(Exception):
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pass
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class WrongHREADYOUTSequence(Exception):
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pass
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class HTRANS(Enum):
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IDLE = 0
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@ -59,24 +65,47 @@ class AMBA3AHBLiteDriver:
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await RisingEdge(self._dut.clk)
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while True:
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# Save address from previous phase
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previous_address = hex(self._dut.HADDR.value)
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if self._dut.HREADYOUT.value:
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# Save address from previous phase
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previous_address = int(self._dut.HADDR.value)
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# Set data for dataphase
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self._dut.HWDATA <= (value >> (nbytes_cnt * 8))
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# Set data for dataphase
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self._dut.HWDATA <= (value >> (nbytes_cnt * 8))
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# Check if we are done in next phase
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if (nbytes_cnt := nbytes_cnt + step_size) >= nbytes:
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self._dut.HTRANS <= HTRANS.IDLE.value
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# Check if we are done in next phase
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if (nbytes_cnt := nbytes_cnt + step_size) >= nbytes:
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self._dut.HTRANS <= HTRANS.IDLE.value
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else:
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# Update address
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self._dut.HADDR <= self._dut.HADDR.value + step_size
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# Wait for next clock cycle
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await RisingEdge(self._dut.clk)
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# Save into dictionary
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write_dict[previous_address] = int(self._dut.HWDATA.value)
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# If HREADYOUT == 0 immediately after the first address phase
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# this is illegal
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elif nbytes_cnt == 0:
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raise WrongHREADYOUTSequence
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# If the slave is not yet ready, just wait
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else:
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# Update address
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self._dut.HADDR <= self._dut.HADDR.value + step_size
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await RisingEdge(self._dut.clk)
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continue
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# Wait for next clock cycle
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await RisingEdge(self._dut.clk)
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# Check for error condition
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if self._dut.HRESP.value:
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if self._dut.HREADYOUT.value:
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raise WrongErrorSequence
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await RisingEdge(self._dut.clk)
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if self._dut.HREADYOUT.value:
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raise BusErrorResponse
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raise WrongErrorSequence
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# Save into dictionary
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write_dict[previous_address] = hex(self._dut.HWDATA.value)
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if nbytes_cnt >= nbytes:
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break
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@ -113,21 +142,42 @@ class AMBA3AHBLiteDriver:
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await RisingEdge(self._dut.clk)
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while True:
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# Save address from previous phase
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previous_address = hex(self._dut.HADDR.value)
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if self._dut.HREADYOUT.value:
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# Save address from previous phase
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previous_address = int(self._dut.HADDR.value)
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# Check if we are done in next phase
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if (nbytes_cnt := nbytes_cnt + step_size) >= nbytes:
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self._dut.HTRANS <= HTRANS.IDLE.value
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# Check if we are done in next phase
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if (nbytes_cnt := nbytes_cnt + step_size) >= nbytes:
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self._dut.HTRANS <= HTRANS.IDLE.value
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else:
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# Update address
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self._dut.HADDR <= self._dut.HADDR.value + step_size
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# Wait for next clock cycle
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await RisingEdge(self._dut.clk)
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# Save into dictionary
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read_dict[previous_address] = int(self._dut.HRDATA.value)
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# If HREADYOUT == 0 immediately after the first address phase
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# this is illegal
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elif nbytes_cnt == 0:
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raise WrongHREADYOUTSequence
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# If the slave is not yet ready, just wait
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else:
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# Update address
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self._dut.HADDR <= self._dut.HADDR.value + step_size
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await RisingEdge(self._dut.clk)
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continue
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# Wait for next clock cycle
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await RisingEdge(self._dut.clk)
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# Check for error condition
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if self._dut.HRESP.value:
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if self._dut.HREADYOUT.value:
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raise WrongErrorSequence
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# Save into dictionary
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read_dict[previous_address] = hex(self._dut.HRDATA.value)
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await RisingEdge(self._dut.clk)
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if self._dut.HREADYOUT.value:
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raise BusErrorResponse
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raise WrongErrorSequence
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if nbytes_cnt >= nbytes:
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break
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@ -1,12 +1,13 @@
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from enum import Enum
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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import cocotb
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import random
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from libs import AMBA3AHBLiteDriver
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@cocotb.test()
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async def test_simple_rw_reg(dut):
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async def test_ahb_access(dut):
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"""Test writing via the bus and reading back"""
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clock = Clock(dut.clk, 1, units="ns") # Create a 10us period clock on port clk
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@ -47,5 +48,141 @@ async def test_simple_rw_reg(dut):
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assert write_dict == read_dict, "Read and write values differ!"
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@cocotb.test()
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async def test_hw_access(dut):
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"""Test writing via the hardware interface
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and reading it back.
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"""
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clock = Clock(dut.clk, 1, units="ns") # Create a 10us period clock on port clk
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cocotb.fork(clock.start()) # Start the clock
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bus = AMBA3AHBLiteDriver.AMBA3AHBLiteDriver(dut=dut, nbytes=4)
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await bus.reset()
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write_dict = {}
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read_dict = {}
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# TODO: At this point, CocoTB has issues with single dimension unpacked but
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# multidimensional packed arrays. Only check first dimension
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dut.register_0__f1_hw_wr <= 1
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dut.register_0__f2_hw_wr <= 1
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rand_val = []
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for addr in (0, 2):
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# Save value that was written in dictionary
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write_dict[addr] = random.randint(0, (1 << 16)-1)
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dut.register_0__f2_in <= [write_dict[2], 0] #, write_dict[6]]
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dut.register_0__f1_in <= [write_dict[0], 0] #, write_dict[4]]
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await RisingEdge(dut.clk)
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dut.register_0__f1_hw_wr <= 0
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dut.register_0__f2_hw_wr <= 0
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for addr in range(0, 4, 2):
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read_dict.update(
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await bus.read(
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address=addr,
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nbytes=2,
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step_size=2))
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dut._log.info(f"Wrote dictionary {write_dict}")
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dut._log.info(f"Read back dictionary {read_dict}")
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assert write_dict == read_dict, "Read and write values differ!"
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@cocotb.test()
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async def test_hw_access_hw_wr_inactive(dut):
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"""Test writing via the hardware interface but
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keeping the write-enable 0. The value that is
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read back should *not* be the same as the value
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that was fed by the testbench.
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"""
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clock = Clock(dut.clk, 1, units="ns") # Create a 10us period clock on port clk
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cocotb.fork(clock.start()) # Start the clock
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bus = AMBA3AHBLiteDriver.AMBA3AHBLiteDriver(dut=dut, nbytes=4)
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await bus.reset()
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write_dict = {}
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read_dict = {}
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# Force initial value
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dut.register_0__f1_q <= [0, 0]
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dut.register_0__f2_q <= [0, 0]
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# Disable write
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dut.register_0__f1_hw_wr <= 0
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dut.register_0__f2_hw_wr <= 0
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rand_val = []
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for addr in (0, 2, 4, 6):
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# Save value that was written in dictionary
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write_dict[addr] = random.randint(0, (1 << 16)-1)
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dut.register_0__f2_in <= [write_dict[2], write_dict[6]]
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dut.register_0__f1_in <= [write_dict[0], write_dict[4]]
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await RisingEdge(dut.clk)
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dut.register_0__f1_hw_wr <= 0
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dut.register_0__f2_hw_wr <= 0
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for addr in range(0, 8, 2):
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read_dict.update(
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await bus.read(
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address=addr,
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nbytes=2,
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step_size=2))
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dut._log.info(f"Wrote dictionary {write_dict}")
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dut._log.info(f"Read back dictionary {read_dict}")
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assert write_dict != read_dict, "Read and write values differ!"
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@cocotb.test()
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async def test_illegal_address(dut):
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"""Test reading and writing to an illegal address.
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The logic should return a correct error sequence.
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"""
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clock = Clock(dut.clk, 1, units="ns") # Create a 10us period clock on port clk
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cocotb.fork(clock.start()) # Start the clock
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bus = AMBA3AHBLiteDriver.AMBA3AHBLiteDriver(dut=dut, nbytes=4)
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await bus.reset()
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rand_addr = random.randint(8, 1337)
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rand_val = random.randint(0, (1 << 32)-1)
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dut._log.info(f"Write value {rand_val} to illegal addres {rand_addr}.")
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write_error = False
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try:
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await bus.write(
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address=rand_addr,
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value=rand_val,
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nbytes=4,
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step_size=4)
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except AMBA3AHBLiteDriver.BusErrorResponse:
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write_error = True
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assert write_error == True, "Write to illegal address did not return an error!"
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read_error = False
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try:
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await bus.read(
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address=rand_addr,
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nbytes=4,
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step_size=4)
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except AMBA3AHBLiteDriver.BusErrorResponse:
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read_error = True
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assert read_error == True, "Read from illegal address did not return an error!"
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