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Fix bug in bus-width of amba3ahblite-widget's instantiation

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This commit is contained in:
Dennis Potter 2021-10-06 23:28:48 -07:00
parent ace4238ccf
commit 57d8050d56
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 3 additions and 3 deletions
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2
srdl2sv/components/addrmap.py
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@ -270,7 +270,7 @@ class AddrMap(Component):
return self.process_yaml(
self.widget_templ_dict['module_instantiation'],
{'bus_width': self.regwidth-1}
{'bus_width': self.regwidth}
)

4
srdl2sv/components/widgets/srdl2sv_amba3ahblite.yaml
View File

@ -56,7 +56,7 @@ module_instantiation:
- name: 'HTRANS'
signal_type: '[1:0]'
- name: 'HWDATA'
signal_type: '[{bus_width}:0]'
signal_type: '[{bus_width}-1:0]'
- name: 'HSEL'
signal_type: ''
output_ports:
@ -65,4 +65,4 @@ module_instantiation:
- name: 'HRESP'
signal_type: ''
- name: 'HRDATA'
signal_type: '[{bus_width}:0]'
signal_type: '[{bus_width}-1:0]'