Fix bug in bus-width of amba3ahblite-widget's instantiation

This commit is contained in:
2021-10-06 23:28:48 -07:00
parent ace4238ccf
commit 57d8050d56
2 changed files with 3 additions and 3 deletions

View File

@@ -270,7 +270,7 @@ class AddrMap(Component):
return self.process_yaml(
self.widget_templ_dict['module_instantiation'],
{'bus_width': self.regwidth-1}
{'bus_width': self.regwidth}
)

View File

@@ -56,7 +56,7 @@ module_instantiation:
- name: 'HTRANS'
signal_type: '[1:0]'
- name: 'HWDATA'
signal_type: '[{bus_width}:0]'
signal_type: '[{bus_width}-1:0]'
- name: 'HSEL'
signal_type: ''
output_ports:
@@ -65,4 +65,4 @@ module_instantiation:
- name: 'HRESP'
signal_type: ''
- name: 'HRDATA'
signal_type: '[{bus_width}:0]'
signal_type: '[{bus_width}-1:0]'