Fix bug in bus-width of amba3ahblite-widget's instantiation

srdl2sv/components/addrmap.py

@@ -270,7 +270,7 @@ class AddrMap(Component):
 
         return self.process_yaml(
             self.widget_templ_dict['module_instantiation'],
-            {'bus_width': self.regwidth-1}
+            {'bus_width': self.regwidth}
         )
 
 

srdl2sv/components/widgets/srdl2sv_amba3ahblite.yaml

@@ -56,7 +56,7 @@ module_instantiation:
         - name: 'HTRANS'
           signal_type: '[1:0]'
         - name: 'HWDATA'
-          signal_type: '[{bus_width}:0]'
+          signal_type: '[{bus_width}-1:0]'
         - name: 'HSEL'
           signal_type: ''
     output_ports:
@@ -65,4 +65,4 @@ module_instantiation:
         - name: 'HRESP'
           signal_type: ''
         - name: 'HRDATA'
-          signal_type: '[{bus_width}:0]'
+          signal_type: '[{bus_width}-1:0]'