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Add option to disable byte-enables

This commit is contained in:
Dennis Potter 2021-10-18 23:48:14 -07:00
parent 4d3f302a54
commit 5e47ff664a
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
4 changed files with 40 additions and 16 deletions
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28
srdl2sv/cli/cli.py
View File

@ -86,12 +86,19 @@ class CliArguments():
in one level of indentation. (default: %(default)s)")
self.parser.add_argument(
"-i",
"--include_desc",
"-c",
"--descriptions",
type=int,
default=0,
help="Include descriptions of addrmaps (+8), regfiles (+4), registers \
(+2), and fields (+1) in RTL. This is a bitfield.")
help="Include descriptions of addrmaps (+16), regfiles (+8), memories (+4) \
registers (+2), and fields (+1) in RTL. This is a bitfield.")
self.parser.add_argument(
"--no_byte_enable",
action="store_true",
help="If this flag gets set, byte-enables get disabled. At that point, it \
is only possible to address whole registers, not single bytes within \
these registers anymore.")
self.parser.add_argument(
"IN_RDL",
@ -158,13 +165,18 @@ class CliArguments():
if args.bus == 'amba3ahblite':
config['addrwidth'] = 32
# Byte enables?
config['no_byte_enable'] = args.no_byte_enable
config['list_args'].append(f"Byte enables : {not config['no_byte_enable']}")
# Set location where descirptions shall be set
# Comparison to 1 to get a Python bool
config['descriptions'] = {}
config['descriptions']['addrmap'] = (args.include_desc >> 3) & 1 == 1
config['descriptions']['regfile'] = (args.include_desc >> 2) & 1 == 1
config['descriptions']['field'] = (args.include_desc >> 1) & 1 == 1
config['descriptions']['register'] = (args.include_desc >> 0) & 1 == 1
config['descriptions']['AddrMap'] = (args.descriptions >> 4) & 1 == 1
config['descriptions']['RegFile'] = (args.descriptions >> 3) & 1 == 1
config['descriptions']['Memory'] = (args.descriptions >> 2) & 1 == 1
config['descriptions']['Register'] = (args.descriptions >> 1) & 1 == 1
config['descriptions']['Field'] = (args.descriptions >> 0) & 1 == 1
config['list_args'].append(f"Descriptions : {config['descriptions']}")
# Set version

4
srdl2sv/components/addrmap.py
View File

@ -295,7 +295,9 @@ class AddrMap(Component):
return self.process_yaml(
self.widget_templ_dict['module_instantiation'],
{'bus_width': self.regwidth}
{'bus_width': self.regwidth,
'no_byte_enable': 1 if self.config['no_byte_enable'] else 0,
}
)

21
srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv
View File

@ -27,7 +27,8 @@ module srdl2sv_amba3ahblite
import srdl2sv_if_pkg::*;
#(
parameter bit FLOP_REGISTER_IF = 0,
parameter BUS_BITS = 32
parameter BUS_BITS = 32,
parameter NO_BYTE_ENABLE = 0
)
(
// Outputs to internal logic
@ -256,13 +257,21 @@ module srdl2sv_amba3ahblite
logic b2r_w_vld_next;
logic b2r_r_vld_next;
always_comb
generate
if (NO_BYTE_ENABLE)
begin
for (int i = 0; i < BUS_BYTES; i++)
HSIZE_bitfielded[i] = i < (1 << HSIZE_q);
assign b2r_byte_en_next = {BUS_BYTES{1'b1}};
end
else
begin
always_comb
begin
for (int i = 0; i < BUS_BYTES; i++)
HSIZE_bitfielded[i] = i < (1 << HSIZE_q);
// Shift if not the full bus is accessed
b2r_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
// Shift if not the full bus is accessed
b2r_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
end
end
/***

3
srdl2sv/components/widgets/srdl2sv_amba3ahblite.yaml
View File

@ -13,7 +13,8 @@ module_instantiation:
*******************************************************************/
srdl2sv_amba3ahblite
#(.FLOP_REGISTER_IF (0),
.BUS_BITS ({bus_width}))
.BUS_BITS ({bus_width}),
.NO_BYTE_ENABLE ({no_byte_enable}))
srdl2sv_amba3ahblite_inst
(// Outputs to internal logic
.b2r,