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Update examples with changes from e46e51f and a148e8b 

The former commit implements fixes that were required for issue #8. The
latter only updated the link to report bugs.
This commit is contained in:
Dennis Potter 2021-10-30 19:38:43 -07:00
parent a148e8bbd1
commit 7efe7c4cea
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
4 changed files with 630 additions and 537 deletions
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6
examples/hierarchical_regfiles/hierarchical_regfiles.rdl
View File

@ -15,9 +15,11 @@ addrmap hierarchical_regfiles {
regfile {
// Remove we property and set hw=w.
// Set sw=r for one of the properties to generate a simple wire
// Set sw=r/hw=r for one of the properties to generate a constant
reg {
field {sw=r; hw=w;} f1 [15:0];
field {sw=rw; hw=w;} f2 [31:16];
field {sw=r; hw=w;} f1 [7:0];
field {sw=r; hw=r;} f2 [15:8] = 42; // It's the meaning of life
field {sw=rw; hw=w;} f3 [31:16];
} reg_c;
// Another level of regfile-hierarchy

63
examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv
View File

@ -20,7 +20,7 @@
*
* Generation information:
* - User: : dpotter
* - Time : October 28 2021 22:54:43
* - Time : October 30 2021 19:38:01
* - Path : /home/dpotter/srdl2sv/examples/hierarchical_regfiles
* - RDL file : ['hierarchical_regfiles.rdl']
* - Hostname : ArchXPS
@ -91,8 +91,8 @@ module hierarchical_regfiles
input logic [15:0] regfile_1__reg_b__f2_in ,
input logic [15:0] regfile_2__regfile_3__reg_d__f1_in[2][4][2],
input logic [15:0] regfile_2__regfile_3__reg_d__f2_in[2][4][2],
input logic [15:0] regfile_2__reg_c__f1_in [2],
input logic [15:0] regfile_2__reg_c__f2_in [2],
input logic [7:0] regfile_2__reg_c__f1_in [2],
input logic [15:0] regfile_2__reg_c__f3_in [2],
input logic reg_e__f1_hw_wr ,
input logic [15:0] reg_e__f1_in ,
input logic reg_e__f2_hw_wr ,
@ -108,6 +108,7 @@ module hierarchical_regfiles
output logic [15:0] regfile_1__reg_b__f2_r ,
output logic [15:0] regfile_2__regfile_3__reg_d__f1_r[2][4][2],
output logic [15:0] regfile_2__regfile_3__reg_d__f2_r[2][4][2],
output logic [7:0] regfile_2__reg_c__f2_r [2],
output logic [15:0] reg_e__f1_r ,
output logic [15:0] reg_e__f2_r
);
@ -188,6 +189,7 @@ assign regfile_1__reg_a_sw_wr = regfile_1__reg_a_active && widget_if.w_vld;
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -216,6 +218,7 @@ assign regfile_1__reg_a__f1_r = regfile_1__reg_a__f1_q;
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -280,6 +283,7 @@ assign regfile_1__reg_b_sw_wr = regfile_1__reg_b_active && widget_if.w_vld;
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -308,6 +312,7 @@ assign regfile_1__reg_b__f1_r = regfile_1__reg_b__f1_q;
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -367,8 +372,9 @@ logic regfile_2__reg_c_sw_wr [2];
logic [31:0] regfile_2__reg_c_data_mux_in[2];
logic regfile_2__reg_c_rdy_mux_in [2];
logic regfile_2__reg_c_err_mux_in [2];
logic [15:0] regfile_2__reg_c__f1_q [2];
logic [15:0] regfile_2__reg_c__f2_q [2];
logic [7:0] regfile_2__reg_c__f1_q [2];
logic [7:0] regfile_2__reg_c__f2_q [2];
logic [15:0] regfile_2__reg_c__f3_q [2];
generate
for (gv_a = 0; gv_a < 2; gv_a++)
@ -406,6 +412,7 @@ begin
// reset : - / -
// flags : ['sw']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -434,6 +441,7 @@ begin
// reset : - / -
// flags : ['sw']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -486,29 +494,44 @@ begin
assign regfile_2__reg_c_sw_wr[gv_a] = regfile_2__reg_c_active[gv_a] && widget_if.w_vld;
//-----------------FIELD SUMMARY-----------------
// name : f1 (regfile_2__reg_c[15:0])
// name : f1 (regfile_2__reg_c[7:0])
// access : hw = w
// sw = r (precedence)
// reset : - / -
// flags : ['sw']
// external : False
// storage type : StorageType.WIRE
//-----------------------------------------------
always_ff @(posedge clk)
begin
// we or wel property not set
regfile_2__reg_c__f1_q[gv_a] <= regfile_2__reg_c__f1_in[gv_a];
end // of regfile_2__reg_c__f1's always_ff
// Field is a simple wire.
// To generate a flop either add the we/wel property, add
// a reset, or change the sw/hw access properties
assign regfile_2__reg_c__f1_q[gv_a] = regfile_2__reg_c__f1_in[gv_a];
//-----------------FIELD SUMMARY-----------------
// name : f2 (regfile_2__reg_c[31:16])
// name : f2 (regfile_2__reg_c[15:8])
// access : hw = r
// sw = r (precedence)
// reset : - / -
// flags : ['sw']
// external : False
// storage type : StorageType.CONST
//-----------------------------------------------
// Field is defined as a constant.
assign regfile_2__reg_c__f2_q[gv_a] = 8'd42;
// Connect register to hardware output port
assign regfile_2__reg_c__f2_r[gv_a] = regfile_2__reg_c__f2_q[gv_a];
//-----------------FIELD SUMMARY-----------------
// name : f3 (regfile_2__reg_c[31:16])
// access : hw = w
// sw = rw (precedence)
// reset : - / -
// flags : ['sw']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -516,14 +539,14 @@ begin
if (regfile_2__reg_c_sw_wr[gv_a])
begin
if (widget_if.byte_en[2])
regfile_2__reg_c__f2_q[gv_a][7:0] <= widget_if.w_data[23:16];
regfile_2__reg_c__f3_q[gv_a][7:0] <= widget_if.w_data[23:16];
if (widget_if.byte_en[3])
regfile_2__reg_c__f2_q[gv_a][15:8] <= widget_if.w_data[31:24];
regfile_2__reg_c__f3_q[gv_a][15:8] <= widget_if.w_data[31:24];
end
else
// we or wel property not set
regfile_2__reg_c__f2_q[gv_a] <= regfile_2__reg_c__f2_in[gv_a];
end // of regfile_2__reg_c__f2's always_ff
regfile_2__reg_c__f3_q[gv_a] <= regfile_2__reg_c__f3_in[gv_a];
end // of regfile_2__reg_c__f3's always_ff
@ -532,7 +555,7 @@ begin
* Assign all fields to signal to Mux *
**************************************/
// Assign all fields. Fields that are not readable are tied to 0.
assign regfile_2__reg_c_data_mux_in[gv_a] = {regfile_2__reg_c__f2_q[gv_a], regfile_2__reg_c__f1_q[gv_a]};
assign regfile_2__reg_c_data_mux_in[gv_a] = {regfile_2__reg_c__f3_q[gv_a], regfile_2__reg_c__f2_q[gv_a], regfile_2__reg_c__f1_q[gv_a]};
// Internal registers are ready immediately
assign regfile_2__reg_c_rdy_mux_in[gv_a] = 1'b1;
@ -573,6 +596,7 @@ assign reg_e_sw_wr = reg_e_active && widget_if.w_vld;
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -601,6 +625,7 @@ assign reg_e__f1_r = reg_e__f1_q;
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)

182
examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv
View File

@ -20,7 +20,7 @@
*
* Generation information:
* - User: : dpotter
* - Time : October 27 2021 23:31:13
* - Time : October 30 2021 19:37:23
* - Path : /home/dpotter/srdl2sv/examples/interrupt_hierarchy
* - RDL file : ['interrupt_hierarchy.rdl']
* - Hostname : ArchXPS
@ -188,12 +188,13 @@ assign block_a_int_sw_wr = block_a_int_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_a_int__crc_error_q <= 0;
block_a_int__crc_error_q <= 1'd0;
end
else
begin
@ -229,12 +230,13 @@ assign block_a_int__crc_error_sticky_latch = block_a_int__crc_error_in;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_a_int__len_error_q <= 0;
block_a_int__len_error_q <= 1'd0;
end
else
begin
@ -270,12 +272,13 @@ assign block_a_int__len_error_sticky_latch = block_a_int__len_error_in;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_a_int__multi_bit_ecc_error_q <= 0;
block_a_int__multi_bit_ecc_error_q <= 1'd0;
end
else
begin
@ -311,12 +314,13 @@ assign block_a_int__multi_bit_ecc_error_sticky_latch = block_a_int__multi_bit_ec
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'sticky']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_a_int__active_ecc_master_q <= 0;
block_a_int__active_ecc_master_q <= 4'd0;
end
else
begin
@ -392,12 +396,13 @@ assign block_a_int_en_sw_wr = block_a_int_en_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_a_int_en__crc_error_q <= 1;
block_a_int_en__crc_error_q <= 1'd1;
end
else
begin
@ -417,12 +422,13 @@ end // of block_a_int_en__crc_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_a_int_en__len_error_q <= 1;
block_a_int_en__len_error_q <= 1'd1;
end
else
begin
@ -442,12 +448,13 @@ end // of block_a_int_en__len_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_a_int_en__multi_bit_ecc_error_q <= 0;
block_a_int_en__multi_bit_ecc_error_q <= 1'd0;
end
else
begin
@ -504,12 +511,13 @@ assign block_a_halt_en_sw_wr = block_a_halt_en_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_a_halt_en__crc_error_q <= 0;
block_a_halt_en__crc_error_q <= 1'd0;
end
else
begin
@ -529,12 +537,13 @@ end // of block_a_halt_en__crc_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_a_halt_en__len_error_q <= 0;
block_a_halt_en__len_error_q <= 1'd0;
end
else
begin
@ -554,12 +563,13 @@ end // of block_a_halt_en__len_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_a_halt_en__multi_bit_ecc_error_q <= 1;
block_a_halt_en__multi_bit_ecc_error_q <= 1'd1;
end
else
begin
@ -621,12 +631,13 @@ assign block_b_int_sw_wr = block_b_int_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_b_int__crc_error_q <= 0;
block_b_int__crc_error_q <= 1'd0;
end
else
begin
@ -662,12 +673,13 @@ assign block_b_int__crc_error_sticky_latch = block_b_int__crc_error_in;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_b_int__len_error_q <= 0;
block_b_int__len_error_q <= 1'd0;
end
else
begin
@ -703,12 +715,13 @@ assign block_b_int__len_error_sticky_latch = block_b_int__len_error_in;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_b_int__multi_bit_ecc_error_q <= 0;
block_b_int__multi_bit_ecc_error_q <= 1'd0;
end
else
begin
@ -744,12 +757,13 @@ assign block_b_int__multi_bit_ecc_error_sticky_latch = block_b_int__multi_bit_ec
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'sticky']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_b_int__active_ecc_master_q <= 0;
block_b_int__active_ecc_master_q <= 4'd0;
end
else
begin
@ -825,12 +839,13 @@ assign block_b_int_en_sw_wr = block_b_int_en_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_b_int_en__crc_error_q <= 1;
block_b_int_en__crc_error_q <= 1'd1;
end
else
begin
@ -850,12 +865,13 @@ end // of block_b_int_en__crc_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_b_int_en__len_error_q <= 1;
block_b_int_en__len_error_q <= 1'd1;
end
else
begin
@ -875,12 +891,13 @@ end // of block_b_int_en__len_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_b_int_en__multi_bit_ecc_error_q <= 0;
block_b_int_en__multi_bit_ecc_error_q <= 1'd0;
end
else
begin
@ -937,12 +954,13 @@ assign block_b_halt_en_sw_wr = block_b_halt_en_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_b_halt_en__crc_error_q <= 0;
block_b_halt_en__crc_error_q <= 1'd0;
end
else
begin
@ -962,12 +980,13 @@ end // of block_b_halt_en__crc_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_b_halt_en__len_error_q <= 0;
block_b_halt_en__len_error_q <= 1'd0;
end
else
begin
@ -987,12 +1006,13 @@ end // of block_b_halt_en__len_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_b_halt_en__multi_bit_ecc_error_q <= 1;
block_b_halt_en__multi_bit_ecc_error_q <= 1'd1;
end
else
begin
@ -1054,12 +1074,13 @@ assign block_c_int_sw_wr = block_c_int_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_c_int__crc_error_q <= 0;
block_c_int__crc_error_q <= 1'd0;
end
else
begin
@ -1095,12 +1116,13 @@ assign block_c_int__crc_error_sticky_latch = block_c_int__crc_error_in;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_c_int__len_error_q <= 0;
block_c_int__len_error_q <= 1'd0;
end
else
begin
@ -1136,12 +1158,13 @@ assign block_c_int__len_error_sticky_latch = block_c_int__len_error_in;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_c_int__multi_bit_ecc_error_q <= 0;
block_c_int__multi_bit_ecc_error_q <= 1'd0;
end
else
begin
@ -1177,12 +1200,13 @@ assign block_c_int__multi_bit_ecc_error_sticky_latch = block_c_int__multi_bit_ec
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'sticky']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_c_int__active_ecc_master_q <= 0;
block_c_int__active_ecc_master_q <= 4'd0;
end
else
begin
@ -1258,12 +1282,13 @@ assign block_c_int_en_sw_wr = block_c_int_en_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_c_int_en__crc_error_q <= 1;
block_c_int_en__crc_error_q <= 1'd1;
end
else
begin
@ -1283,12 +1308,13 @@ end // of block_c_int_en__crc_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_c_int_en__len_error_q <= 1;
block_c_int_en__len_error_q <= 1'd1;
end
else
begin
@ -1308,12 +1334,13 @@ end // of block_c_int_en__len_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_c_int_en__multi_bit_ecc_error_q <= 0;
block_c_int_en__multi_bit_ecc_error_q <= 1'd0;
end
else
begin
@ -1370,12 +1397,13 @@ assign block_c_halt_en_sw_wr = block_c_halt_en_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_c_halt_en__crc_error_q <= 0;
block_c_halt_en__crc_error_q <= 1'd0;
end
else
begin
@ -1395,12 +1423,13 @@ end // of block_c_halt_en__crc_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_c_halt_en__len_error_q <= 0;
block_c_halt_en__len_error_q <= 1'd0;
end
else
begin
@ -1420,12 +1449,13 @@ end // of block_c_halt_en__len_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_c_halt_en__multi_bit_ecc_error_q <= 1;
block_c_halt_en__multi_bit_ecc_error_q <= 1'd1;
end
else
begin
@ -1487,12 +1517,13 @@ assign block_d_int_sw_wr = block_d_int_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_d_int__crc_error_q <= 0;
block_d_int__crc_error_q <= 1'd0;
end
else
begin
@ -1528,12 +1559,13 @@ assign block_d_int__crc_error_sticky_latch = block_d_int__crc_error_in;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_d_int__len_error_q <= 0;
block_d_int__len_error_q <= 1'd0;
end
else
begin
@ -1569,12 +1601,13 @@ assign block_d_int__len_error_sticky_latch = block_d_int__len_error_in;
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'intr', 'intr type', 'enable', 'haltenable']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_d_int__multi_bit_ecc_error_q <= 0;
block_d_int__multi_bit_ecc_error_q <= 1'd0;
end
else
begin
@ -1610,12 +1643,13 @@ assign block_d_int__multi_bit_ecc_error_sticky_latch = block_d_int__multi_bit_ec
// reset : active_low / asynchronous
// flags : ['sw', 'woclr', 'desc', 'sticky']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_d_int__active_ecc_master_q <= 0;
block_d_int__active_ecc_master_q <= 4'd0;
end
else
begin
@ -1691,12 +1725,13 @@ assign block_d_int_en_sw_wr = block_d_int_en_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_d_int_en__crc_error_q <= 1;
block_d_int_en__crc_error_q <= 1'd1;
end
else
begin
@ -1716,12 +1751,13 @@ end // of block_d_int_en__crc_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_d_int_en__len_error_q <= 1;
block_d_int_en__len_error_q <= 1'd1;
end
else
begin
@ -1741,12 +1777,13 @@ end // of block_d_int_en__len_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_d_int_en__multi_bit_ecc_error_q <= 0;
block_d_int_en__multi_bit_ecc_error_q <= 1'd0;
end
else
begin
@ -1803,12 +1840,13 @@ assign block_d_halt_en_sw_wr = block_d_halt_en_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_d_halt_en__crc_error_q <= 0;
block_d_halt_en__crc_error_q <= 1'd0;
end
else
begin
@ -1828,12 +1866,13 @@ end // of block_d_halt_en__crc_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_d_halt_en__len_error_q <= 0;
block_d_halt_en__len_error_q <= 1'd0;
end
else
begin
@ -1853,12 +1892,13 @@ end // of block_d_halt_en__len_error's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
block_d_halt_en__multi_bit_ecc_error_q <= 1;
block_d_halt_en__multi_bit_ecc_error_q <= 1'd1;
end
else
begin
@ -1914,12 +1954,13 @@ assign master_int_active = widget_if.addr == 4096;
// reset : active_low / asynchronous
// flags : ['intr', 'stickybit', 'sw', 'desc', 'enable', 'next']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_int__module_a_int_q <= 0;
master_int__module_a_int_q <= 1'd0;
end
else
begin
@ -1938,12 +1979,13 @@ end // of master_int__module_a_int's always_ff
// reset : active_low / asynchronous
// flags : ['intr', 'stickybit', 'sw', 'desc', 'enable', 'next']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_int__module_b_int_q <= 0;
master_int__module_b_int_q <= 1'd0;
end
else
begin
@ -1962,12 +2004,13 @@ end // of master_int__module_b_int's always_ff
// reset : active_low / asynchronous
// flags : ['intr', 'stickybit', 'sw', 'desc', 'enable', 'next']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_int__module_c_int_q <= 0;
master_int__module_c_int_q <= 1'd0;
end
else
begin
@ -1986,12 +2029,13 @@ end // of master_int__module_c_int's always_ff
// reset : active_low / asynchronous
// flags : ['intr', 'stickybit', 'sw', 'desc', 'enable', 'next']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_int__module_d_int_q <= 0;
master_int__module_d_int_q <= 1'd0;
end
else
begin
@ -2051,12 +2095,13 @@ assign master_halt_active = widget_if.addr == 4100;
// reset : active_low / asynchronous
// flags : ['intr', 'stickybit', 'sw', 'desc', 'haltenable', 'next']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_halt__module_a_int_q <= 0;
master_halt__module_a_int_q <= 1'd0;
end
else
begin
@ -2075,12 +2120,13 @@ end // of master_halt__module_a_int's always_ff
// reset : active_low / asynchronous
// flags : ['intr', 'stickybit', 'sw', 'desc', 'haltenable', 'next']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_halt__module_b_int_q <= 0;
master_halt__module_b_int_q <= 1'd0;
end
else
begin
@ -2099,12 +2145,13 @@ end // of master_halt__module_b_int's always_ff
// reset : active_low / asynchronous
// flags : ['intr', 'stickybit', 'sw', 'desc', 'haltenable', 'next']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_halt__module_c_int_q <= 0;
master_halt__module_c_int_q <= 1'd0;
end
else
begin
@ -2123,12 +2170,13 @@ end // of master_halt__module_c_int's always_ff
// reset : active_low / asynchronous
// flags : ['intr', 'stickybit', 'sw', 'desc', 'haltenable', 'next']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_halt__module_d_int_q <= 0;
master_halt__module_d_int_q <= 1'd0;
end
else
begin
@ -2193,12 +2241,13 @@ assign master_int_en_sw_wr = master_int_en_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_int_en__module_a_int_en_q <= 0;
master_int_en__module_a_int_en_q <= 1'd0;
end
else
begin
@ -2218,12 +2267,13 @@ end // of master_int_en__module_a_int_en's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_int_en__module_b_int_en_q <= 0;
master_int_en__module_b_int_en_q <= 1'd0;
end
else
begin
@ -2243,12 +2293,13 @@ end // of master_int_en__module_b_int_en's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_int_en__module_c_int_en_q <= 0;
master_int_en__module_c_int_en_q <= 1'd0;
end
else
begin
@ -2268,12 +2319,13 @@ end // of master_int_en__module_c_int_en's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_int_en__module_d_int_en_q <= 0;
master_int_en__module_d_int_en_q <= 1'd0;
end
else
begin
@ -2331,12 +2383,13 @@ assign master_halt_en_sw_wr = master_halt_en_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_halt_en__module_a_halt_en_q <= 0;
master_halt_en__module_a_halt_en_q <= 1'd0;
end
else
begin
@ -2356,12 +2409,13 @@ end // of master_halt_en__module_a_halt_en's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_halt_en__module_b_halt_en_q <= 0;
master_halt_en__module_b_halt_en_q <= 1'd0;
end
else
begin
@ -2381,12 +2435,13 @@ end // of master_halt_en__module_b_halt_en's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_halt_en__module_c_halt_en_q <= 0;
master_halt_en__module_c_halt_en_q <= 1'd0;
end
else
begin
@ -2406,12 +2461,13 @@ end // of master_halt_en__module_c_halt_en's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
master_halt_en__module_d_halt_en_q <= 0;
master_halt_en__module_d_halt_en_q <= 1'd0;
end
else
begin
@ -2465,12 +2521,13 @@ assign global_int_active = widget_if.addr == 4112;
// reset : active_low / asynchronous
// flags : ['sw', 'intr', 'stickybit', 'desc', 'enable', 'next']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
global_int__global_int_q <= 0;
global_int__global_int_q <= 1'd0;
end
else
begin
@ -2489,12 +2546,13 @@ end // of global_int__global_int's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'intr', 'stickybit', 'desc', 'haltenable', 'next']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
global_int__global_halt_q <= 0;
global_int__global_halt_q <= 1'd0;
end
else
begin
@ -2557,12 +2615,13 @@ assign global_int_en_sw_wr = global_int_en_active && widget_if.w_vld;
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
global_int_en__global_int_en_q <= 0;
global_int_en__global_int_en_q <= 1'd0;
end
else
begin
@ -2582,12 +2641,13 @@ end // of global_int_en__global_int_en's always_ff
// reset : active_low / asynchronous
// flags : ['sw', 'desc']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk or negedge field_reset_n)
if (!field_reset_n)
begin
global_int_en__global_halt_en_q <= 0;
global_int_en__global_halt_en_q <= 1'd0;
end
else
begin

8
examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv
View File

@ -20,7 +20,7 @@
*
* Generation information:
* - User: : dpotter
* - Time : October 27 2021 23:33:01
* - Time : October 30 2021 19:37:29
* - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg
* - RDL file : ['simple_rw_reg.rdl']
* - Hostname : ArchXPS
@ -174,6 +174,7 @@ assign register_1d_sw_wr = register_1d_active && widget_if.w_vld;
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -202,6 +203,7 @@ assign register_1d__f1_r = register_1d__f1_q;
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -269,6 +271,7 @@ begin
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -297,6 +300,7 @@ begin
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -370,6 +374,7 @@ begin
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
@ -398,6 +403,7 @@ begin
// reset : - / -
// flags : ['sw', 'we']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)