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Update examples with changes from a43cd2e (issue #7)

This commit is contained in:
Dennis Potter 2021-10-31 16:00:00 -07:00
parent a43cd2ea6c
commit 82b2490256
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
5 changed files with 161 additions and 103 deletions
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19
examples/enums/srdl2sv_out/enums.sv
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@ -20,7 +20,7 @@
* *
* Generation information: * Generation information:
* - User: : dpotter * - User: : dpotter
* - Time : October 31 2021 13:59:16 * - Time : October 31 2021 16:01:37
* - Path : /home/dpotter/srdl2sv/examples/enums * - Path : /home/dpotter/srdl2sv/examples/enums
* - RDL file : ['enums.rdl'] * - RDL file : ['enums.rdl']
* - Hostname : ArchXPS * - Hostname : ArchXPS
@ -35,6 +35,7 @@
* - Use Real Tabs : False * - Use Real Tabs : False
* - Tab Width : 4 * - Tab Width : 4
* - Enums Enabled : True * - Enums Enabled : True
* - Unpacked I/Os : True
* - Register Bus Type: amba3ahblite * - Register Bus Type: amba3ahblite
* - Address width : 32 * - Address width : 32
* - Byte enables : True * - Byte enables : True
@ -83,26 +84,26 @@ module enums
input [32-1:0] HWDATA , input [32-1:0] HWDATA ,
input HSEL , input HSEL ,
input enums_pkg::third_enum regfile_1__reg_c__f1_in, input enums_pkg::third_enum regfile_1__reg_c__f1_in,
input logic [1:0] regfile_1__reg_c__f2_in, input [1:0] regfile_1__reg_c__f2_in,
input enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_in, input enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_in,
input logic [1:0] regfile_1__reg_d__f2_in, input [1:0] regfile_1__reg_d__f2_in,
input enums_pkg::first_enum reg_a__f1_in , input enums_pkg::first_enum reg_a__f1_in ,
input logic [1:0] reg_a__f2_in , input [1:0] reg_a__f2_in ,
input enums_pkg::second_enum reg_b__f1_in , input enums_pkg::second_enum reg_b__f1_in ,
input logic [1:0] reg_b__f2_in , input [1:0] reg_b__f2_in ,
// Outputs // Outputs
output HREADYOUT , output HREADYOUT ,
output HRESP , output HRESP ,
output [32-1:0] HRDATA , output [32-1:0] HRDATA ,
output enums_pkg::third_enum regfile_1__reg_c__f1_r, output enums_pkg::third_enum regfile_1__reg_c__f1_r,
output logic [1:0] regfile_1__reg_c__f2_r, output [1:0] regfile_1__reg_c__f2_r,
output enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_r, output enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_r,
output logic [1:0] regfile_1__reg_d__f2_r, output [1:0] regfile_1__reg_d__f2_r,
output enums_pkg::first_enum reg_a__f1_r , output enums_pkg::first_enum reg_a__f1_r ,
output logic [1:0] reg_a__f2_r , output [1:0] reg_a__f2_r ,
output enums_pkg::second_enum reg_b__f1_r , output enums_pkg::second_enum reg_b__f1_r ,
output logic [1:0] reg_b__f2_r output [1:0] reg_b__f2_r
); );

2
examples/hierarchical_regfiles/hierarchical_regfiles.rdl
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@ -30,7 +30,7 @@ addrmap hierarchical_regfiles {
field {sw=rw; hw=rw;} f2 [31:16]; field {sw=rw; hw=rw;} f2 [31:16];
} reg_d; } reg_d;
} regfile_3 [4][2]; } regfile_3 [4][2];
} regfile_2 [2]; } regfile_2 [3];
// Just a plain old register // Just a plain old register
reg { reg {

143
examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv
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@ -20,7 +20,7 @@
* *
* Generation information: * Generation information:
* - User: : dpotter * - User: : dpotter
* - Time : October 30 2021 23:34:40 * - Time : October 31 2021 15:59:23
* - Path : /home/dpotter/srdl2sv/examples/hierarchical_regfiles * - Path : /home/dpotter/srdl2sv/examples/hierarchical_regfiles
* - RDL file : ['hierarchical_regfiles.rdl'] * - RDL file : ['hierarchical_regfiles.rdl']
* - Hostname : ArchXPS * - Hostname : ArchXPS
@ -35,6 +35,7 @@
* - Use Real Tabs : False * - Use Real Tabs : False
* - Tab Width : 4 * - Tab Width : 4
* - Enums Enabled : True * - Enums Enabled : True
* - Unpacked I/Os : True
* - Register Bus Type: amba3ahblite * - Register Bus Type: amba3ahblite
* - Address width : 32 * - Address width : 32
* - Byte enables : True * - Byte enables : True
@ -81,36 +82,36 @@ module hierarchical_regfiles
input [1:0] HTRANS , input [1:0] HTRANS ,
input [32-1:0] HWDATA , input [32-1:0] HWDATA ,
input HSEL , input HSEL ,
input logic regfile_1__reg_a__f1_hw_wr , input regfile_1__reg_a__f1_hw_wr ,
input logic [15:0] regfile_1__reg_a__f1_in , input [15:0] regfile_1__reg_a__f1_in ,
input logic regfile_1__reg_a__f2_hw_wr , input regfile_1__reg_a__f2_hw_wr ,
input logic [15:0] regfile_1__reg_a__f2_in , input [15:0] regfile_1__reg_a__f2_in ,
input logic regfile_1__reg_b__f1_hw_wr , input regfile_1__reg_b__f1_hw_wr ,
input logic [15:0] regfile_1__reg_b__f1_in , input [15:0] regfile_1__reg_b__f1_in ,
input logic regfile_1__reg_b__f2_hw_wr , input regfile_1__reg_b__f2_hw_wr ,
input logic [15:0] regfile_1__reg_b__f2_in , input [15:0] regfile_1__reg_b__f2_in ,
input logic [15:0] regfile_2__regfile_3__reg_d__f1_in[2][4][2], input [15:0] regfile_2__regfile_3__reg_d__f1_in[3][4][2],
input logic [15:0] regfile_2__regfile_3__reg_d__f2_in[2][4][2], input [15:0] regfile_2__regfile_3__reg_d__f2_in[3][4][2],
input logic [7:0] regfile_2__reg_c__f1_in [2], input [7:0] regfile_2__reg_c__f1_in [3],
input logic [15:0] regfile_2__reg_c__f3_in [2], input [15:0] regfile_2__reg_c__f3_in [3],
input logic reg_e__f1_hw_wr , input reg_e__f1_hw_wr ,
input logic [15:0] reg_e__f1_in , input [15:0] reg_e__f1_in ,
input logic reg_e__f2_hw_wr , input reg_e__f2_hw_wr ,
input logic [15:0] reg_e__f2_in , input [15:0] reg_e__f2_in ,
// Outputs // Outputs
output HREADYOUT , output HREADYOUT ,
output HRESP , output HRESP ,
output [32-1:0] HRDATA , output [32-1:0] HRDATA ,
output logic [15:0] regfile_1__reg_a__f1_r , output [15:0] regfile_1__reg_a__f1_r ,
output logic [15:0] regfile_1__reg_a__f2_r , output [15:0] regfile_1__reg_a__f2_r ,
output logic [15:0] regfile_1__reg_b__f1_r , output [15:0] regfile_1__reg_b__f1_r ,
output logic [15:0] regfile_1__reg_b__f2_r , output [15:0] regfile_1__reg_b__f2_r ,
output logic [15:0] regfile_2__regfile_3__reg_d__f1_r[2][4][2], output [15:0] regfile_2__regfile_3__reg_d__f1_r[3][4][2],
output logic [15:0] regfile_2__regfile_3__reg_d__f2_r[2][4][2], output [15:0] regfile_2__regfile_3__reg_d__f2_r[3][4][2],
output logic [7:0] regfile_2__reg_c__f2_r [2], output [7:0] regfile_2__reg_c__f2_r [3],
output logic [15:0] reg_e__f1_r , output [15:0] reg_e__f1_r ,
output logic [15:0] reg_e__f2_r output [15:0] reg_e__f2_r
); );
@ -352,32 +353,32 @@ assign regfile_1__reg_b_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0]
******************************************************************* *******************************************************************
* REGFILE : regfile_2 * REGFILE : regfile_2
* DIMENSION : 1 * DIMENSION : 1
* DEPTHS (per dimension): [2] * DEPTHS (per dimension): [3]
******************************************************************* *******************************************************************
*******************************************************************/ *******************************************************************/
// Variables of register 'reg_d' // Variables of register 'reg_d'
logic regfile_2__regfile_3__reg_d_active [2][4][2]; logic regfile_2__regfile_3__reg_d_active [3][4][2];
logic regfile_2__regfile_3__reg_d_sw_wr [2][4][2]; logic regfile_2__regfile_3__reg_d_sw_wr [3][4][2];
logic [31:0] regfile_2__regfile_3__reg_d_data_mux_in[2][4][2]; logic [31:0] regfile_2__regfile_3__reg_d_data_mux_in[3][4][2];
logic regfile_2__regfile_3__reg_d_rdy_mux_in [2][4][2]; logic regfile_2__regfile_3__reg_d_rdy_mux_in [3][4][2];
logic regfile_2__regfile_3__reg_d_err_mux_in [2][4][2]; logic regfile_2__regfile_3__reg_d_err_mux_in [3][4][2];
logic [15:0] regfile_2__regfile_3__reg_d__f1_q [2][4][2]; logic [15:0] regfile_2__regfile_3__reg_d__f1_q [3][4][2];
logic [15:0] regfile_2__regfile_3__reg_d__f2_q [2][4][2]; logic [15:0] regfile_2__regfile_3__reg_d__f2_q [3][4][2];
// Variables of register 'reg_c' // Variables of register 'reg_c'
logic regfile_2__reg_c_active [2]; logic regfile_2__reg_c_active [3];
logic regfile_2__reg_c_sw_wr [2]; logic regfile_2__reg_c_sw_wr [3];
logic [31:0] regfile_2__reg_c_data_mux_in[2]; logic [31:0] regfile_2__reg_c_data_mux_in[3];
logic regfile_2__reg_c_rdy_mux_in [2]; logic regfile_2__reg_c_rdy_mux_in [3];
logic regfile_2__reg_c_err_mux_in [2]; logic regfile_2__reg_c_err_mux_in [3];
logic [7:0] regfile_2__reg_c__f1_q [2]; logic [7:0] regfile_2__reg_c__f1_q [3];
logic [7:0] regfile_2__reg_c__f2_q [2]; logic [7:0] regfile_2__reg_c__f2_q [3];
logic [15:0] regfile_2__reg_c__f3_q [2]; logic [15:0] regfile_2__reg_c__f3_q [3];
generate generate
for (gv_a = 0; gv_a < 2; gv_a++) for (gv_a = 0; gv_a < 3; gv_a++)
begin begin
/******************************************************************* /*******************************************************************
******************************************************************* *******************************************************************
@ -586,7 +587,7 @@ logic [15:0] reg_e__f2_q ;
// Register-activation for 'reg_e' // Register-activation for 'reg_e'
assign reg_e_active = widget_if.addr == 136; assign reg_e_active = widget_if.addr == 172;
assign reg_e_sw_wr = reg_e_active && widget_if.w_vld; assign reg_e_sw_wr = reg_e_active && widget_if.w_vld;
//-----------------FIELD SUMMARY----------------- //-----------------FIELD SUMMARY-----------------
@ -774,6 +775,54 @@ begin
widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[1][3][1]; widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[1][3][1];
widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[1][3][1]; widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[1][3][1];
end end
regfile_2__regfile_3__reg_d_active[2][0][0]:
begin
widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][0][0];
widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][0][0];
widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][0][0];
end
regfile_2__regfile_3__reg_d_active[2][0][1]:
begin
widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][0][1];
widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][0][1];
widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][0][1];
end
regfile_2__regfile_3__reg_d_active[2][1][0]:
begin
widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][1][0];
widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][1][0];
widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][1][0];
end
regfile_2__regfile_3__reg_d_active[2][1][1]:
begin
widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][1][1];
widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][1][1];
widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][1][1];
end
regfile_2__regfile_3__reg_d_active[2][2][0]:
begin
widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][2][0];
widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][2][0];
widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][2][0];
end
regfile_2__regfile_3__reg_d_active[2][2][1]:
begin
widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][2][1];
widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][2][1];
widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][2][1];
end
regfile_2__regfile_3__reg_d_active[2][3][0]:
begin
widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][3][0];
widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][3][0];
widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][3][0];
end
regfile_2__regfile_3__reg_d_active[2][3][1]:
begin
widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][3][1];
widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][3][1];
widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][3][1];
end
regfile_2__reg_c_active[0]: regfile_2__reg_c_active[0]:
begin begin
widget_if.r_data = regfile_2__reg_c_data_mux_in[0]; widget_if.r_data = regfile_2__reg_c_data_mux_in[0];
@ -786,6 +835,12 @@ begin
widget_if.err = regfile_2__reg_c_err_mux_in[1]; widget_if.err = regfile_2__reg_c_err_mux_in[1];
widget_if.rdy = regfile_2__reg_c_rdy_mux_in[1]; widget_if.rdy = regfile_2__reg_c_rdy_mux_in[1];
end end
regfile_2__reg_c_active[2]:
begin
widget_if.r_data = regfile_2__reg_c_data_mux_in[2];
widget_if.err = regfile_2__reg_c_err_mux_in[2];
widget_if.rdy = regfile_2__reg_c_rdy_mux_in[2];
end
reg_e_active: reg_e_active:
begin begin
widget_if.r_data = reg_e_data_mux_in; widget_if.r_data = reg_e_data_mux_in;

61
examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv
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@ -20,7 +20,7 @@
* *
* Generation information: * Generation information:
* - User: : dpotter * - User: : dpotter
* - Time : October 30 2021 23:34:49 * - Time : October 31 2021 15:59:28
* - Path : /home/dpotter/srdl2sv/examples/interrupt_hierarchy * - Path : /home/dpotter/srdl2sv/examples/interrupt_hierarchy
* - RDL file : ['interrupt_hierarchy.rdl'] * - RDL file : ['interrupt_hierarchy.rdl']
* - Hostname : ArchXPS * - Hostname : ArchXPS
@ -35,6 +35,7 @@
* - Use Real Tabs : False * - Use Real Tabs : False
* - Tab Width : 4 * - Tab Width : 4
* - Enums Enabled : True * - Enums Enabled : True
* - Unpacked I/Os : True
* - Register Bus Type: amba3ahblite * - Register Bus Type: amba3ahblite
* - Address width : 32 * - Address width : 32
* - Byte enables : True * - Byte enables : True
@ -81,40 +82,40 @@ module interrupt_hierarchy
input [1:0] HTRANS , input [1:0] HTRANS ,
input [32-1:0] HWDATA , input [32-1:0] HWDATA ,
input HSEL , input HSEL ,
input logic [0:0] block_a_int__crc_error_in , input [0:0] block_a_int__crc_error_in ,
input logic [0:0] block_a_int__len_error_in , input [0:0] block_a_int__len_error_in ,
input logic [0:0] block_a_int__multi_bit_ecc_error_in, input [0:0] block_a_int__multi_bit_ecc_error_in,
input logic [3:0] block_a_int__active_ecc_master_in , input [3:0] block_a_int__active_ecc_master_in ,
input logic [0:0] block_b_int__crc_error_in , input [0:0] block_b_int__crc_error_in ,
input logic [0:0] block_b_int__len_error_in , input [0:0] block_b_int__len_error_in ,
input logic [0:0] block_b_int__multi_bit_ecc_error_in, input [0:0] block_b_int__multi_bit_ecc_error_in,
input logic [3:0] block_b_int__active_ecc_master_in , input [3:0] block_b_int__active_ecc_master_in ,
input logic [0:0] block_c_int__crc_error_in , input [0:0] block_c_int__crc_error_in ,
input logic [0:0] block_c_int__len_error_in , input [0:0] block_c_int__len_error_in ,
input logic [0:0] block_c_int__multi_bit_ecc_error_in, input [0:0] block_c_int__multi_bit_ecc_error_in,
input logic [3:0] block_c_int__active_ecc_master_in , input [3:0] block_c_int__active_ecc_master_in ,
input logic [0:0] block_d_int__crc_error_in , input [0:0] block_d_int__crc_error_in ,
input logic [0:0] block_d_int__len_error_in , input [0:0] block_d_int__len_error_in ,
input logic [0:0] block_d_int__multi_bit_ecc_error_in, input [0:0] block_d_int__multi_bit_ecc_error_in,
input logic [3:0] block_d_int__active_ecc_master_in , input [3:0] block_d_int__active_ecc_master_in ,
// Outputs // Outputs
output HREADYOUT , output HREADYOUT ,
output HRESP , output HRESP ,
output [32-1:0] HRDATA , output [32-1:0] HRDATA ,
output logic block_a_int_intr, output block_a_int_intr,
output logic block_a_int_halt, output block_a_int_halt,
output logic block_b_int_intr, output block_b_int_intr,
output logic block_b_int_halt, output block_b_int_halt,
output logic block_c_int_intr, output block_c_int_intr,
output logic block_c_int_halt, output block_c_int_halt,
output logic block_d_int_intr, output block_d_int_intr,
output logic block_d_int_halt, output block_d_int_halt,
output logic master_int_intr , output master_int_intr ,
output logic master_halt_intr, output master_halt_intr,
output logic master_halt_halt, output master_halt_halt,
output logic global_int_intr , output global_int_intr ,
output logic global_int_halt output global_int_halt
); );

39
examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv
View File

@ -20,7 +20,7 @@
* *
* Generation information: * Generation information:
* - User: : dpotter * - User: : dpotter
* - Time : October 30 2021 23:34:53 * - Time : October 31 2021 15:59:35
* - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg * - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg
* - RDL file : ['simple_rw_reg.rdl'] * - RDL file : ['simple_rw_reg.rdl']
* - Hostname : ArchXPS * - Hostname : ArchXPS
@ -35,6 +35,7 @@
* - Use Real Tabs : False * - Use Real Tabs : False
* - Tab Width : 4 * - Tab Width : 4
* - Enums Enabled : True * - Enums Enabled : True
* - Unpacked I/Os : True
* - Register Bus Type: amba3ahblite * - Register Bus Type: amba3ahblite
* - Address width : 32 * - Address width : 32
* - Byte enables : True * - Byte enables : True
@ -81,29 +82,29 @@ module simple_rw_reg
input [1:0] HTRANS , input [1:0] HTRANS ,
input [32-1:0] HWDATA , input [32-1:0] HWDATA ,
input HSEL , input HSEL ,
input logic register_1d__f1_hw_wr, input register_1d__f1_hw_wr,
input logic [15:0] register_1d__f1_in , input [15:0] register_1d__f1_in ,
input logic register_1d__f2_hw_wr, input register_1d__f2_hw_wr,
input logic [15:0] register_1d__f2_in , input [15:0] register_1d__f2_in ,
input logic register_2d__f1_hw_wr[2], input register_2d__f1_hw_wr[2],
input logic [15:0] register_2d__f1_in [2], input [15:0] register_2d__f1_in [2],
input logic register_2d__f2_hw_wr[2], input register_2d__f2_hw_wr[2],
input logic [15:0] register_2d__f2_in [2], input [15:0] register_2d__f2_in [2],
input logic register_3d__f1_hw_wr[2][2], input register_3d__f1_hw_wr[2][2],
input logic [15:0] register_3d__f1_in [2][2], input [15:0] register_3d__f1_in [2][2],
input logic register_3d__f2_hw_wr[2][2], input register_3d__f2_hw_wr[2][2],
input logic [15:0] register_3d__f2_in [2][2], input [15:0] register_3d__f2_in [2][2],
// Outputs // Outputs
output HREADYOUT , output HREADYOUT ,
output HRESP , output HRESP ,
output [32-1:0] HRDATA , output [32-1:0] HRDATA ,
output logic [15:0] register_1d__f1_r, output [15:0] register_1d__f1_r,
output logic [15:0] register_1d__f2_r, output [15:0] register_1d__f2_r,
output logic [15:0] register_2d__f1_r[2], output [15:0] register_2d__f1_r[2],
output logic [15:0] register_2d__f2_r[2], output [15:0] register_2d__f2_r[2],
output logic [15:0] register_3d__f1_r[2][2], output [15:0] register_3d__f1_r[2][2],
output logic [15:0] register_3d__f2_r[2][2] output [15:0] register_3d__f2_r[2][2]
); );