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https://github.com/Silicon1602/srdl2sv.git
synced 2024-11-14 11:03:36 +00:00
Repair multi-enumerations in one regfile bug
When a regfile did use enumerations from multiple scopes this messed up the eventual packages because every regfile only assumed 1 scope. This is fixed now. TODO: Check what happens if enums are defined in the register scope.
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d3bfdeb3f0
commit
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@ -303,11 +303,12 @@ class AddrMap(Component):
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# First go through all registers in this scope to generate a package
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# First go through all registers in this scope to generate a package
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package_rtl = []
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package_rtl = []
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enum_rtl = []
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rtl_return = dict()
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rtl_return = dict()
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# Need to keep track of enum names since they shall be unique
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# Need to keep track of enum names since they shall be unique
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# per scope
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# per scope
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enum_rtl = dict()
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enum_rtl[self.name] = []
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enum_members = dict()
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enum_members = dict()
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for i in self.registers.values():
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for i in self.registers.values():
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@ -344,26 +345,33 @@ class AddrMap(Component):
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max_name_width = max_name_width,
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max_name_width = max_name_width,
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name = var[0]))
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name = var[0]))
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enum_rtl.append(
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enum_rtl[self.name].append(
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AddrMap.templ_dict['enum_declaration']['rtl'].format(
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AddrMap.templ_dict['enum_declaration']['rtl'].format(
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width=value.width-1,
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width=value.width-1,
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name = key,
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name = key,
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enum_var_list = ',\n'.join(variable_list)))
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enum_var_list = ',\n'.join(variable_list)))
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package_rtl =\
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AddrMap.templ_dict['package_declaration']['rtl'].format(
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name = self.name,
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pkg_content = '\n\n'.join(enum_rtl))
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rtl_return[self.name] = AddrMap.add_tabs(
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package_rtl,
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tab_width,
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real_tabs)
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# Invoke get_package_rtl method from regfiles
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# Invoke get_package_rtl method from regfiles
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[rtl_return.update(x.get_package_rtl(tab_width, real_tabs))
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for regfile in self.regfiles.values():
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for x in self.regfiles.values()]
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for key, value in regfile.get_package_rtl().items():
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if key in enum_rtl:
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enum_rtl[key] = [*enum_rtl[key], *value]
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else:
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enum_rtl[key] = value
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# Create RTL to return
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for key, value in enum_rtl.items():
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package_rtl =\
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AddrMap.templ_dict['package_declaration']['rtl'].format(
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name = key,
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pkg_content = '\n\n'.join(enum_rtl[key]))
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rtl_return[key] = AddrMap.add_tabs(
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package_rtl,
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tab_width,
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real_tabs)
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return rtl_return
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return rtl_return
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@ -200,25 +200,23 @@ class RegFile(Component):
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return names
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return names
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def get_package_rtl(self, tab_width: int = 4, real_tabs = False) -> dict():
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def get_package_rtl(self) -> dict():
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if not self.config['enums']:
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if not self.config['enums']:
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return None
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return None
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# First go through all registers in this scope to generate a package
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# First go through all registers in this scope to generate a package
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package_rtl = []
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package_rtl = []
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enum_rtl = []
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enum_rtl = dict()
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rtl_return = list()
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rtl_return = list()
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# Need to keep track of enum names since they shall be unique
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# Need to keep track of enum names since they shall be unique
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# per scope
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# per scope
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enum_members = dict()
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enum_members = dict()
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enum_found = False
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for i in self.registers.values():
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for i in self.registers.values():
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for key, value in i.get_typedefs().items():
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for key, value in i.get_typedefs().items():
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if not enum_found:
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if value.scope not in enum_rtl:
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enum_found = True
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enum_rtl[value.scope] = []
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scope = value.scope
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variable_list = []
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variable_list = []
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@ -241,7 +239,7 @@ class RegFile(Component):
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"Exiting...".format(
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"Exiting...".format(
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var[0],
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var[0],
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enum_members[var[0]],
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enum_members[var[0]],
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"::".join([self.name, key])))
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"::".join([value.scope, key])))
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sys.exit(1)
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sys.exit(1)
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@ -252,27 +250,13 @@ class RegFile(Component):
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max_name_width = max_name_width,
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max_name_width = max_name_width,
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name = var[0]))
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name = var[0]))
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enum_rtl.append(
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enum_rtl[value.scope].append(
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RegFile.templ_dict['enum_declaration']['rtl'].format(
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RegFile.templ_dict['enum_declaration']['rtl'].format(
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width=value.width-1,
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width=value.width-1,
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name = key,
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name = key,
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enum_var_list = ',\n'.join(variable_list)))
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enum_var_list = ',\n'.join(variable_list)))
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if enum_found:
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return enum_rtl
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package_rtl =\
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RegFile.templ_dict['package_declaration']['rtl'].format(
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name = scope,
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pkg_content = '\n\n'.join(enum_rtl))
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return {scope:
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RegFile.add_tabs(
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package_rtl,
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tab_width,
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real_tabs)
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}
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else:
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return {None: None}
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def get_regwidth(self) -> int:
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def get_regwidth(self) -> int:
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return self.regwidth
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return self.regwidth
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