Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-12-21 22:48:41 +00:00
Code Issues Projects Releases Wiki Activity

Closes #10: sw read/write side-effects now honor byte-enables if enabled

Browse Source
This commit is contained in:
Dennis Potter 2021-10-31 22:36:51 -07:00
parent 22a822c097
commit 8df25ece01
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 54 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
srdl2sv/components/field.py
View File

@ -139,22 +139,9 @@ class Field(Component):
)
# Check if an onwrite property is set
onwrite = obj.get_property('onwrite')
if onwrite:
if onwrite == OnWriteType.wuser:
self.logger.warning("The OnWriteType.wuser is not yet supported!")
elif onwrite in (OnWriteType.wclr, OnWriteType.wset):
access_rtl['sw_write'][0].append(
self._process_yaml(
Field.templ_dict[str(onwrite)],
{'path': path_underscored,
'genvars': self.genvars_str,
'width': obj.width,
'path_wo_field': path_wo_field,
'field_type': self.field_type}
)
)
if onwrite := obj.get_property('onwrite'):
if onwrite is OnWriteType.wuser:
self.logger.error("The OnWriteType.wuser is not yet supported!")
else:
# If field spans multiple bytes, every byte shall have a seperate enable!
for i in range(self.lsbyte, self.msbyte+1):
@ -167,7 +154,7 @@ class Field(Component):
{'path': path_underscored,
'genvars': self.genvars_str,
'i': i,
'width': obj.width,
'width': msb_bus - lsb_bus + 1,
'msb_bus': str(msb_bus),
'lsb_bus': str(lsb_bus),
'msb_field': str(msb_bus-obj.inst.lsb),
@ -216,14 +203,30 @@ class Field(Component):
access_rtl['sw_read'][0].append(
self._process_yaml(
Field.templ_dict[str(onread)],
{'width': obj.width,
'path': path_underscored,
Field.templ_dict['sw_read_access_field'],
{'path_wo_field': path_wo_field,
'genvars': self.genvars_str,
'path_wo_field': path_wo_field}
'field_type': self.field_type}
)
)
# If field spans multiple bytes, every byte shall have a seperate enable!
for i in range(self.lsbyte, self.msbyte+1):
access_rtl['sw_read'][0].append(
self._process_yaml(
Field.templ_dict[str(onread)],
{'path': path_underscored,
'genvars': self.genvars_str,
'i': i,
'width': msb_bus - lsb_bus + 1,
'msb_field': str(msb_bus-obj.inst.lsb),
'lsb_field': str(lsb_bus-obj.inst.lsb),
}
)
)
access_rtl['sw_read'][0].append("end")
# Add singlepulse property
# Property cannot be overwritten by alias
if obj.get_property('singlepulse'):

51
srdl2sv/components/templates/fields.yaml
View File

@ -133,52 +133,61 @@ end_field_ff:
OnWriteType.woset:
rtl: |-
if (widget_if.byte_en[{i}]) // woset property
begin
<<INDENT>>
{path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] | widget_if.w_data[{msb_bus}:{lsb_bus}];
end
<<UNINDENT>>
OnWriteType.woclr:
rtl: |-
if (widget_if.byte_en[{i}]) // woclr property
begin
<<INDENT>>
{path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] & ~widget_if.w_data[{msb_bus}:{lsb_bus}];
end
<<UNINDENT>>
OnWriteType.wot:
rtl: |-
if (widget_if.byte_en[{i}]) // wot property
begin
<<INDENT>>
{path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] ^ widget_if.w_data[{msb_bus}:{lsb_bus}];
end
<<UNINDENT>>
OnWriteType.wzs:
rtl: |-
if (widget_if.byte_en[{i}]) // wzs property
begin
<<INDENT>>
{path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] & widget_if.w_data[{msb_bus}:{lsb_bus}];
end
<<UNINDENT>>
OnWriteType.wzt:
rtl: |-
if (widget_if.byte_en[{i}]) // wzt property
begin
<<INDENT>>
{path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] ~^ widget_if.w_data[{msb_bus}:{lsb_bus}];
end
<<UNINDENT>>
OnWriteType.wclr:
rtl: |-
{path}_q{genvars} <= {{{width}{{1'b0}}}};
if (widget_if.byte_en[{i}]) // wclr property
<<INDENT>>
{path}_q{genvars}[{msb_field}:{lsb_field}] <= {width}'b0;
<<UNINDENT>>
OnWriteType.wset:
rtl: |-
{path}_q{genvars} <= {{{width}{{1'b1}}}};
if (widget_if.byte_en[{i}]) // wclr property
<<INDENT>>
{path}_q{genvars}[{msb_field}:{lsb_field}] <= {{{width}{{1'b1}}}};
<<UNINDENT>>
sw_read_access_field:
rtl: |-
if ({path_wo_field}_sw_rd{genvars})
begin
OnReadType.rclr:
rtl: |-
if ({path_wo_field}_sw_rd{genvars}) // rclr property
begin
{path}_q{genvars} <= {{{width}{{1'b0}}}};
end
if (widget_if.byte_en[{i}]) // rclr property
<<INDENT>>
{path}_q{genvars}[{msb_field}:{lsb_field}] <= {width}'b0;
<<UNINDENT>>
OnReadType.rset:
rtl: |-
if ({path_wo_field}_sw_rd{genvars}) // rset property
begin
{path}_q{genvars} <= {{{width}{{1'b1}}}};
end
if (widget_if.byte_en[{i}]) // rset property
<<INDENT>>
{path}_q{genvars}[{msb_field}:{lsb_field}] <= {{{width}{{1'b1}}}};
<<UNINDENT>>
field_comment:
rtl: |-