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https://github.com/Silicon1602/srdl2sv.git
synced 2024-12-22 06:58:41 +00:00
Fix AMBA AHB 3 Lite widget so that first register transactions succeed
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186A8AD440942BAF
8
.gitignore
vendored
8
.gitignore
vendored
@ -1,4 +1,9 @@
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# Grabbed from https://github.com/github/gitignore/blob/master/Python.gitignore on 05/02/2021
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# SRDL2SV specific
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srdl2sv_out
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###############################################################################################
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# Grabbed from https://github.com/github/gitignore/blob/master/Python.gitignore on 05/02/2021 #
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###############################################################################################
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# Byte-compiled / optimized / DLL files
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__pycache__/
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@ -138,4 +143,3 @@ dmypy.json
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# Cython debug symbols
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cython_debug/
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@ -1 +1,4 @@
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systemrdl-compiler==1.19.0
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cocotb
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cocotb-bus
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PyYAML
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@ -26,34 +26,35 @@
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module srdl2sv_amba3ahblite
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import srdl2sv_if_pkg::*;
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#(
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parameter bit FLOP_REGISTER_IF = 0
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parameter bit FLOP_REGISTER_IF = 0,
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parameter BUS_BITS = 32
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)
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(
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// Outputs to internal logic
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output b2r_t b2r,
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output b2r_t b2r,
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// Inputs from internal logic
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input r2b_t r2b,
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input r2b_t r2b,
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// Bus protocol
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input HCLK,
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input HRESETn,
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input HSEL,
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input [31:0] HADDR,
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input HWRITE,
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input [ 2:0] HSIZE,
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input [ 2:0] HBURST,
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input [ 3:0] HPROT,
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input [ 1:0] HTRANS,
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input [31:0] HWDATA,
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input HREADY,
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input HMASTLOCK,
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input HCLK,
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input HRESETn,
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input HSEL,
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input [31:0] HADDR,
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input HWRITE,
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input [ 2:0] HSIZE,
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input [ 3:0] HPROT, // Might be used in the future together with an RDL UDP
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input [ 1:0] HTRANS,
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input [BUS_BITS-1:0] HWDATA,
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output logic HREADYOUT,
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output logic HRESP,
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output logic [31:0] HRDATA
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output logic HREADYOUT,
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output logic HRESP,
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output logic [BUS_BITS-1:0] HRDATA
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);
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localparam BUS_BYTES = BUS_BITS/8;
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localparam BUS_BYTES_W = $clog2(BUS_BYTES);
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/***********************
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* Define enums
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***********************/
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@ -85,13 +86,11 @@ module srdl2sv_amba3ahblite
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WRITE = 1'b1
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} OP_t;
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typedef enum logic [2:0] {
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FSM_IDLE = 3'b000,
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FSM_NONSEQ= 3'b001,
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FSM_SEQ = 3'b010,
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FSM_WAIT = 3'b011,
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FSM_ERR_0 = 3'b100,
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FSM_ERR_1 = 3'b101
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typedef enum logic [1:0] {
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FSM_IDLE = 2'b00,
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FSM_TRANS = 2'b01,
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FSM_ERR_0 = 2'b10,
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FSM_ERR_1 = 2'b11
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} fsm_t;
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/****************************
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@ -100,7 +99,7 @@ module srdl2sv_amba3ahblite
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logic [31:0] addr_q;
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OP_t operation_q;
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wire addr_err = (HADDR[2:0] % HSIZE) != 3'b0;
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wire addr_err = HADDR % (32'b1 << HSIZE) != 32'b0;
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always_ff @ (posedge HCLK)
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begin
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@ -113,16 +112,16 @@ module srdl2sv_amba3ahblite
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// of extending the address phase of the next transfer
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if (HREADYOUT)
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begin
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addr_q <= HADDR;
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// Floor address. Sub-register access will be handled by byte-enables
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addr_q <= {HADDR[BUS_BITS-1:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
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operation_q <= HWRITE ? WRITE : READ;
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end
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end
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SEQ:
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begin
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if (HREADYOUT)
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begin
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addr_q <= addr_q; // TODO
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end
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// Floor address. Sub-register access will be handled by byte-enables
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addr_q <= {HADDR[BUS_BITS-1:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
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end
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endcase
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end
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@ -153,16 +152,15 @@ module srdl2sv_amba3ahblite
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fsm_next = FSM_ERR_0;
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else if (HTRANS == NONSEQ)
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// If NONSEQ, go to NONSEQ state
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fsm_next = FSM_NONSEQ;
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fsm_next = FSM_TRANS;
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else if (HTRANS == SEQ)
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// If a SEQ is provided, something is wrong
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fsm_next = FSM_ERR_0;
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end
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end
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FSM_NONSEQ:
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FSM_TRANS:
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begin
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HREADYOUT = r2b.rdy;
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b2r_w_vld_next = operation_q == WRITE;
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b2r_r_vld_next = operation_q == READ;
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@ -173,30 +171,24 @@ module srdl2sv_amba3ahblite
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else if (HTRANS == BUSY)
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begin
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// Wait
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fsm_next = FSM_NONSEQ;
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fsm_next = FSM_TRANS;
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end
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else if (HTRANS == NONSEQ)
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begin
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// Another unrelated access is coming
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fsm_next = FSM_NONSEQ;
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fsm_next = FSM_TRANS;
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end
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else if (HTRANS == SEQ)
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begin
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// Entering a burst
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fsm_next = r2b.rdy ? FSM_SEQ : FSM_NONSEQ;
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// Another part of the burst is coming
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fsm_next = FSM_TRANS;
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end
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else if (HTRANS == IDLE)
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begin
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// All done, wrapping things up!
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fsm_next = r2b.rdy ? FSM_IDLE : FSM_NONSEQ;
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fsm_next = r2b.rdy ? FSM_IDLE : FSM_TRANS;
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end
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end
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FSM_SEQ:
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begin
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end
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FSM_WAIT:
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begin
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end
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FSM_ERR_0:
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begin
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HREADYOUT = 0;
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@ -205,21 +197,32 @@ module srdl2sv_amba3ahblite
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begin
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// Slaves must always provide a zero wait state OKAY response
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// to BUSY transfers and the transfer must be ignored by the slave.
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HRESP = 0;
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HRESP = OKAY;
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fsm_next = FSM_ERR_0;
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end
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else
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begin
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HRESP = 1;
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HRESP = ERROR;
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fsm_next = FSM_ERR_1;
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end
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end
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FSM_ERR_1:
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begin
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HREADYOUT = 1;
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HRESP = 1;
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if (HTRANS == BUSY)
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begin
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// Slaves must always provide a zero wait state OKAY response
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// to BUSY transfers and the transfer must be ignored by the slave.
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HREADYOUT = 0;
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HRESP = OKAY;
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fsm_next = FSM_ERR_0;
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end
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else
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begin
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HREADYOUT = 1;
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HRESP = ERROR;
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fsm_next = FSM_IDLE;
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fsm_next = FSM_IDLE;
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end
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end
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endcase
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end
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@ -234,19 +237,19 @@ module srdl2sv_amba3ahblite
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/***
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* Determine the number of active bytes
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***/
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logic [3:0] HSIZE_bitfielded;
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logic [3:0] b2r_byte_en_next;
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logic b2r_w_vld_next;
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logic b2r_r_vld_next;
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//always_comb
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//begin
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// case (HTRANS)
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// 3'b000 : b2r_byte_en_next = 4'b0001;
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// 3'b001 : b2r_byte_en_next = 4'b0011;
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// 3'b010 : b2r_byte_en_next = 4'b1111;
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// default: b2r_byte_en_next = 4'b1111;
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// endcase
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//end
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always_comb
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begin
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for (int i = 0; i < BUS_BYTES; i++)
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HSIZE_bitfielded[i] = i < (1 << HSIZE);
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// Shift if not the full bus is accessed
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b2r_byte_en_next = HSIZE_bitfielded << (HADDR % BUS_BYTES);
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end
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/***
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* Drive interface to registers
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@ -269,7 +272,7 @@ module srdl2sv_amba3ahblite
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always_ff @ (posedge HCLK)
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begin
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b2r.addr <= addr_q;
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b2r.data <= HWDATA;
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b2r.data <= HWDATA << HADDR[BUS_BYTES_W-1:0];
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b2r.byte_en <= b2r_byte_en_next;
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end
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end
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@ -278,7 +281,7 @@ module srdl2sv_amba3ahblite
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assign b2r.w_vld = b2r_w_vld_next;
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assign b2r.r_vld = b2r_r_vld_next;
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assign b2r.addr = addr_q;
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assign b2r.data = HWDATA;
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assign b2r.data = HWDATA << HADDR[BUS_BYTES_W-1:0];
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assign b2r.byte_en = b2r_byte_en_next;
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end
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endgenerate
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@ -12,6 +12,8 @@ module_instantiation:
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* - clk -> Clock that drives registers and the bus
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*******************************************************************/
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srdl2sv_amba3ahblite
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#(.FLOP_REGISTER_IF (0),
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.BUS_BITS (32))
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srdl2sv_amba3ahblite_inst
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(// Outputs to internal logic
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.b2r,
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@ -25,13 +27,10 @@ module_instantiation:
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.HADDR,
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.HWRITE,
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.HSIZE,
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.HBURST,
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.HPROT,
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.HTRANS,
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.HWDATA,
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.HREADY,
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.HSEL,
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.HMASTLOCK,
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.HREADYOUT,
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.HRESP,
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@ -52,20 +51,14 @@ module_instantiation:
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signal_type: ''
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- name: 'HSIZE'
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signal_type: '[2:0]'
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- name: 'HBURST'
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signal_type: '[2:0]'
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- name: 'HPROT'
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signal_type: '[3:0]'
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- name: 'HTRANS'
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signal_type: '[1:0]'
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- name: 'HWDATA'
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signal_type: '[31:0]'
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- name: 'HREADY'
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signal_type: ''
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- name: 'HSEL'
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signal_type: ''
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- name: 'HMASTLOCK'
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signal_type: ''
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output_ports:
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- name: 'HREADYOUT'
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signal_type: ''
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2
tests/.gitignore
vendored
2
tests/.gitignore
vendored
@ -1,2 +1,2 @@
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srdl2sv_out
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*.fst
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sim_build
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