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Fix AMBA AHB 3 Lite widget so that first register transactions succeed

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This commit is contained in:
Dennis Potter 2021-09-25 13:01:23 -07:00
parent 28edf17a1c
commit 8ea1ad97da
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
5 changed files with 75 additions and 72 deletions
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8
.gitignore vendored
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@ -1,4 +1,9 @@
# Grabbed from https://github.com/github/gitignore/blob/master/Python.gitignore on 05/02/2021 # SRDL2SV specific
srdl2sv_out
###############################################################################################
# Grabbed from https://github.com/github/gitignore/blob/master/Python.gitignore on 05/02/2021 #
###############################################################################################
# Byte-compiled / optimized / DLL files # Byte-compiled / optimized / DLL files
__pycache__/ __pycache__/
@ -138,4 +143,3 @@ dmypy.json
# Cython debug symbols # Cython debug symbols
cython_debug/ cython_debug/

3
requirements.txt
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@ -1 +1,4 @@
systemrdl-compiler==1.19.0 systemrdl-compiler==1.19.0
cocotb
cocotb-bus
PyYAML

123
srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv
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@ -26,34 +26,35 @@
module srdl2sv_amba3ahblite module srdl2sv_amba3ahblite
import srdl2sv_if_pkg::*; import srdl2sv_if_pkg::*;
#( #(
parameter bit FLOP_REGISTER_IF = 0 parameter bit FLOP_REGISTER_IF = 0,
parameter BUS_BITS = 32
) )
( (
// Outputs to internal logic // Outputs to internal logic
output b2r_t b2r, output b2r_t b2r,
// Inputs from internal logic // Inputs from internal logic
input r2b_t r2b, input r2b_t r2b,
// Bus protocol // Bus protocol
input HCLK, input HCLK,
input HRESETn, input HRESETn,
input HSEL, input HSEL,
input [31:0] HADDR, input [31:0] HADDR,
input HWRITE, input HWRITE,
input [ 2:0] HSIZE, input [ 2:0] HSIZE,
input [ 2:0] HBURST, input [ 3:0] HPROT, // Might be used in the future together with an RDL UDP
input [ 3:0] HPROT, input [ 1:0] HTRANS,
input [ 1:0] HTRANS, input [BUS_BITS-1:0] HWDATA,
input [31:0] HWDATA,
input HREADY,
input HMASTLOCK,
output logic HREADYOUT, output logic HREADYOUT,
output logic HRESP, output logic HRESP,
output logic [31:0] HRDATA output logic [BUS_BITS-1:0] HRDATA
); );
localparam BUS_BYTES = BUS_BITS/8;
localparam BUS_BYTES_W = $clog2(BUS_BYTES);
/*********************** /***********************
* Define enums * Define enums
***********************/ ***********************/
@ -85,13 +86,11 @@ module srdl2sv_amba3ahblite
WRITE = 1'b1 WRITE = 1'b1
} OP_t; } OP_t;
typedef enum logic [2:0] { typedef enum logic [1:0] {
FSM_IDLE = 3'b000, FSM_IDLE = 2'b00,
FSM_NONSEQ= 3'b001, FSM_TRANS = 2'b01,
FSM_SEQ = 3'b010, FSM_ERR_0 = 2'b10,
FSM_WAIT = 3'b011, FSM_ERR_1 = 2'b11
FSM_ERR_0 = 3'b100,
FSM_ERR_1 = 3'b101
} fsm_t; } fsm_t;
/**************************** /****************************
@ -100,7 +99,7 @@ module srdl2sv_amba3ahblite
logic [31:0] addr_q; logic [31:0] addr_q;
OP_t operation_q; OP_t operation_q;
wire addr_err = (HADDR[2:0] % HSIZE) != 3'b0; wire addr_err = HADDR % (32'b1 << HSIZE) != 32'b0;
always_ff @ (posedge HCLK) always_ff @ (posedge HCLK)
begin begin
@ -113,16 +112,16 @@ module srdl2sv_amba3ahblite
// of extending the address phase of the next transfer // of extending the address phase of the next transfer
if (HREADYOUT) if (HREADYOUT)
begin begin
addr_q <= HADDR; // Floor address. Sub-register access will be handled by byte-enables
addr_q <= {HADDR[BUS_BITS-1:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
operation_q <= HWRITE ? WRITE : READ; operation_q <= HWRITE ? WRITE : READ;
end end
end end
SEQ: SEQ:
begin begin
if (HREADYOUT) if (HREADYOUT)
begin // Floor address. Sub-register access will be handled by byte-enables
addr_q <= addr_q; // TODO addr_q <= {HADDR[BUS_BITS-1:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
end
end end
endcase endcase
end end
@ -153,16 +152,15 @@ module srdl2sv_amba3ahblite
fsm_next = FSM_ERR_0; fsm_next = FSM_ERR_0;
else if (HTRANS == NONSEQ) else if (HTRANS == NONSEQ)
// If NONSEQ, go to NONSEQ state // If NONSEQ, go to NONSEQ state
fsm_next = FSM_NONSEQ; fsm_next = FSM_TRANS;
else if (HTRANS == SEQ) else if (HTRANS == SEQ)
// If a SEQ is provided, something is wrong // If a SEQ is provided, something is wrong
fsm_next = FSM_ERR_0; fsm_next = FSM_ERR_0;
end end
end end
FSM_NONSEQ: FSM_TRANS:
begin begin
HREADYOUT = r2b.rdy; HREADYOUT = r2b.rdy;
b2r_w_vld_next = operation_q == WRITE; b2r_w_vld_next = operation_q == WRITE;
b2r_r_vld_next = operation_q == READ; b2r_r_vld_next = operation_q == READ;
@ -173,30 +171,24 @@ module srdl2sv_amba3ahblite
else if (HTRANS == BUSY) else if (HTRANS == BUSY)
begin begin
// Wait // Wait
fsm_next = FSM_NONSEQ; fsm_next = FSM_TRANS;
end end
else if (HTRANS == NONSEQ) else if (HTRANS == NONSEQ)
begin begin
// Another unrelated access is coming // Another unrelated access is coming
fsm_next = FSM_NONSEQ; fsm_next = FSM_TRANS;
end end
else if (HTRANS == SEQ) else if (HTRANS == SEQ)
begin begin
// Entering a burst // Another part of the burst is coming
fsm_next = r2b.rdy ? FSM_SEQ : FSM_NONSEQ; fsm_next = FSM_TRANS;
end end
else if (HTRANS == IDLE) else if (HTRANS == IDLE)
begin begin
// All done, wrapping things up! // All done, wrapping things up!
fsm_next = r2b.rdy ? FSM_IDLE : FSM_NONSEQ; fsm_next = r2b.rdy ? FSM_IDLE : FSM_TRANS;
end end
end end
FSM_SEQ:
begin
end
FSM_WAIT:
begin
end
FSM_ERR_0: FSM_ERR_0:
begin begin
HREADYOUT = 0; HREADYOUT = 0;
@ -205,21 +197,32 @@ module srdl2sv_amba3ahblite
begin begin
// Slaves must always provide a zero wait state OKAY response // Slaves must always provide a zero wait state OKAY response
// to BUSY transfers and the transfer must be ignored by the slave. // to BUSY transfers and the transfer must be ignored by the slave.
HRESP = 0; HRESP = OKAY;
fsm_next = FSM_ERR_0; fsm_next = FSM_ERR_0;
end end
else else
begin begin
HRESP = 1; HRESP = ERROR;
fsm_next = FSM_ERR_1; fsm_next = FSM_ERR_1;
end end
end end
FSM_ERR_1: FSM_ERR_1:
begin begin
HREADYOUT = 1; if (HTRANS == BUSY)
HRESP = 1; begin
// Slaves must always provide a zero wait state OKAY response
// to BUSY transfers and the transfer must be ignored by the slave.
HREADYOUT = 0;
HRESP = OKAY;
fsm_next = FSM_ERR_0;
end
else
begin
HREADYOUT = 1;
HRESP = ERROR;
fsm_next = FSM_IDLE; fsm_next = FSM_IDLE;
end
end end
endcase endcase
end end
@ -234,19 +237,19 @@ module srdl2sv_amba3ahblite
/*** /***
* Determine the number of active bytes * Determine the number of active bytes
***/ ***/
logic [3:0] HSIZE_bitfielded;
logic [3:0] b2r_byte_en_next; logic [3:0] b2r_byte_en_next;
logic b2r_w_vld_next; logic b2r_w_vld_next;
logic b2r_r_vld_next; logic b2r_r_vld_next;
//always_comb always_comb
//begin begin
// case (HTRANS) for (int i = 0; i < BUS_BYTES; i++)
// 3'b000 : b2r_byte_en_next = 4'b0001; HSIZE_bitfielded[i] = i < (1 << HSIZE);
// 3'b001 : b2r_byte_en_next = 4'b0011;
// 3'b010 : b2r_byte_en_next = 4'b1111; // Shift if not the full bus is accessed
// default: b2r_byte_en_next = 4'b1111; b2r_byte_en_next = HSIZE_bitfielded << (HADDR % BUS_BYTES);
// endcase end
//end
/*** /***
* Drive interface to registers * Drive interface to registers
@ -269,7 +272,7 @@ module srdl2sv_amba3ahblite
always_ff @ (posedge HCLK) always_ff @ (posedge HCLK)
begin begin
b2r.addr <= addr_q; b2r.addr <= addr_q;
b2r.data <= HWDATA; b2r.data <= HWDATA << HADDR[BUS_BYTES_W-1:0];
b2r.byte_en <= b2r_byte_en_next; b2r.byte_en <= b2r_byte_en_next;
end end
end end
@ -278,7 +281,7 @@ module srdl2sv_amba3ahblite
assign b2r.w_vld = b2r_w_vld_next; assign b2r.w_vld = b2r_w_vld_next;
assign b2r.r_vld = b2r_r_vld_next; assign b2r.r_vld = b2r_r_vld_next;
assign b2r.addr = addr_q; assign b2r.addr = addr_q;
assign b2r.data = HWDATA; assign b2r.data = HWDATA << HADDR[BUS_BYTES_W-1:0];
assign b2r.byte_en = b2r_byte_en_next; assign b2r.byte_en = b2r_byte_en_next;
end end
endgenerate endgenerate

11
srdl2sv/components/widgets/srdl2sv_amba3ahblite.yaml
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@ -12,6 +12,8 @@ module_instantiation:
* - clk -> Clock that drives registers and the bus * - clk -> Clock that drives registers and the bus
*******************************************************************/ *******************************************************************/
srdl2sv_amba3ahblite srdl2sv_amba3ahblite
#(.FLOP_REGISTER_IF (0),
.BUS_BITS (32))
srdl2sv_amba3ahblite_inst srdl2sv_amba3ahblite_inst
(// Outputs to internal logic (// Outputs to internal logic
.b2r, .b2r,
@ -25,13 +27,10 @@ module_instantiation:
.HADDR, .HADDR,
.HWRITE, .HWRITE,
.HSIZE, .HSIZE,
.HBURST,
.HPROT, .HPROT,
.HTRANS, .HTRANS,
.HWDATA, .HWDATA,
.HREADY,
.HSEL, .HSEL,
.HMASTLOCK,
.HREADYOUT, .HREADYOUT,
.HRESP, .HRESP,
@ -52,20 +51,14 @@ module_instantiation:
signal_type: '' signal_type: ''
- name: 'HSIZE' - name: 'HSIZE'
signal_type: '[2:0]' signal_type: '[2:0]'
- name: 'HBURST'
signal_type: '[2:0]'
- name: 'HPROT' - name: 'HPROT'
signal_type: '[3:0]' signal_type: '[3:0]'
- name: 'HTRANS' - name: 'HTRANS'
signal_type: '[1:0]' signal_type: '[1:0]'
- name: 'HWDATA' - name: 'HWDATA'
signal_type: '[31:0]' signal_type: '[31:0]'
- name: 'HREADY'
signal_type: ''
- name: 'HSEL' - name: 'HSEL'
signal_type: '' signal_type: ''
- name: 'HMASTLOCK'
signal_type: ''
output_ports: output_ports:
- name: 'HREADYOUT' - name: 'HREADYOUT'
signal_type: '' signal_type: ''

2
tests/.gitignore vendored
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@ -1,2 +1,2 @@
srdl2sv_out
*.fst *.fst
sim_build