Fix bug with dynamic saturate values and fix Lint warnings
Two categories Lint warnings occured:
- Width mismatches, since integers are 32-bit wide according to the
SV LRM.
- Constant saturate values, because values could get larger than
32-bit and smaller than 0.
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parent
5d3fd14144
commit
8fbf800c4f
GPG Key ID:
186A8AD440942BAF
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@ -87,7 +87,7 @@ class Field(Component):
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access_rtl = {}
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if alias:
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owning_addrmap, full_path, path, path_underscored =\
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_, _, path, path_underscored =\
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Field.create_underscored_path_static(obj)
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else:
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owning_addrmap, full_path, path, path_underscored =\
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@ -264,42 +264,46 @@ class Field(Component):
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# Determine saturation values
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if isinstance(self.obj.get_property('incrsaturate'), bool):
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if self.obj.get_property('incrsaturate'):
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incr_sat_value = 2**self.obj.width-1
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incr_sat_value = f"{self.obj.width}'d{2**self.obj.width-1}"
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overflow_value = incr_sat_value
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else:
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incr_sat_value = False
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overflow_value = 2**self.obj.width-1
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else:
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incr_sat_value = self.obj.get_property('incrsaturate')
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incr_sat_value = self.get_signal_name(
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self.obj.get_property('incrsaturate'))
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overflow_value = incr_sat_value
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if isinstance(self.obj.get_property('decrsaturate'), bool):
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if self.obj.get_property('decrsaturate'):
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decr_sat_value = 0
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decr_sat_value = f"{self.obj.width}'d0"
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underflow_value = decr_sat_value
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else:
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decr_sat_value = False
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underflow_value = 0
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else:
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decr_sat_value = self.obj.get_property('decrsaturate')
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decr_sat_value = self.get_signal_name(
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self.obj.get_property('decrsaturate'))
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underflow_value = decr_sat_value
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# Determine threshold values
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if isinstance(self.obj.get_property('incrthreshold'), bool):
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if self.obj.get_property('incrthreshold'):
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incr_thr_value = 2**self.obj.width-1
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incr_thr_value = f"{self.obj.width}'d{2**self.obj.width-1}"
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else:
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incr_thr_value = False
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else:
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incr_thr_value = self.obj.get_property('incrthreshold')
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incr_thr_value = self.get_signal_name(
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self.obj.get_property('incrthreshold'))
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if isinstance(self.obj.get_property('decrthreshold'), bool):
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if self.obj.get_property('decrthreshold'):
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decr_thr_value = 2**self.obj.width-1
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decr_thr_value = f"{self.obj.width}'d{2**self.obj.width-1}"
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else:
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decr_thr_value = False
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else:
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decr_thr_value = self.obj.get_property('decrthreshold')
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decr_thr_value = self.get_signal_name(
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self.obj.get_property('decrthreshold'))
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# Determine with what value the counter is incremented
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# According to the spec, the incrvalue/decrvalue default to '1'
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@ -428,6 +432,20 @@ class Field(Component):
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"defined. This is not legal and the decrwidth property "
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"will be ignored!")
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# Calculate the number of bits that need to be padded with 0s
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if remaining_width := self.obj.width - incr_width:
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incr_zero_pad = f"{remaining_width}'b0, "
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incr_sat_zero_pad = f"{remaining_width+1}'b0, "
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else:
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incr_zero_pad = ""
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incr_sat_zero_pad = "1'b0"
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if remaining_width := self.obj.width - decr_width:
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decr_zero_pad = f"{remaining_width}'b0, "
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decr_sat_zero_pad = f"{remaining_width+1}'b0, "
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else:
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decr_zero_pad = ''
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decr_sat_zero_pad = "1'b0"
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# If no input is defined for the decrement value, define
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# an internal signal. It is possible that this is tied to 0.
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@ -551,9 +569,10 @@ class Field(Component):
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Field.templ_dict['counter_incr_sat'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width,
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'decr_width': decr_width,
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'sat_value': incr_sat_value,
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'width_plus_1': self.obj.width + 1,
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'incr_sat_zero_pad': incr_sat_zero_pad,
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'decr_sat_zero_pad': decr_sat_zero_pad,
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}
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)
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)
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@ -573,9 +592,10 @@ class Field(Component):
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Field.templ_dict['counter_decr_sat'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width,
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'decr_width': decr_width,
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'sat_value': decr_sat_value,
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'width_plus_1': self.obj.width + 1,
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'incr_sat_zero_pad': incr_sat_zero_pad,
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'decr_sat_zero_pad': decr_sat_zero_pad,
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}
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)
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)
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@ -590,9 +610,10 @@ class Field(Component):
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Field.templ_dict['counter_incr_thr'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width,
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'decr_width': decr_width,
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'thr_value': incr_thr_value,
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'width_plus_1': self.obj.width + 1,
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'incr_sat_zero_pad': incr_sat_zero_pad,
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'decr_sat_zero_pad': incr_sat_zero_pad,
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}
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)
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)
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@ -603,9 +624,10 @@ class Field(Component):
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Field.templ_dict['counter_decr_thr'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width,
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'decr_width': decr_width,
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'thr_value': decr_thr_value,
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'width_plus_1': self.obj.width + 1,
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'incr_sat_zero_pad': incr_sat_zero_pad,
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'decr_sat_zero_pad': decr_sat_zero_pad,
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}
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)
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)
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@ -617,9 +639,10 @@ class Field(Component):
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Field.templ_dict['counter_overflow'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width,
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'decr_width': decr_width,
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'overflow_value': overflow_value,
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'width_plus_1': self.obj.width + 1,
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'incr_sat_zero_pad': incr_sat_zero_pad,
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'decr_sat_zero_pad': decr_sat_zero_pad,
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}
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)
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)
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@ -630,9 +653,10 @@ class Field(Component):
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Field.templ_dict['counter_underflow'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width,
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'decr_width': decr_width,
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'underflow_value': underflow_value,
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'width_plus_1': self.obj.width + 1,
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'incr_sat_zero_pad': incr_sat_zero_pad,
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'decr_sat_zero_pad': decr_sat_zero_pad,
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}
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)
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)
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@ -643,6 +667,8 @@ class Field(Component):
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Field.templ_dict['counter'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_zero_pad': incr_zero_pad,
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'decr_zero_pad': decr_zero_pad,
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}
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)
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)
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@ -1467,6 +1493,12 @@ class Field(Component):
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"field. Note that explicit connecting this "\
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"is not required if a field_reset was defined.")
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if self.obj.get_property('counter') \
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and self.obj.get_property("reset") is None:
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self.logger.warning("Field is a counter but has no reset. "\
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"This should probably be fixed since this "\
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"will result in undefined behavior in simulations.")
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@staticmethod
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def __process_reset_signal(reset_signal):
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@ -281,28 +281,28 @@ counter:
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// might be tied to 0.
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always_comb
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begin
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{path}_next{genvars} = {path}_q{genvars};
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{path}_next{genvars} = {path}_q{genvars};
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if ({path}_incr{genvars} && {path}_decr{genvars})
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begin
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if (!{path}_incr_sat{genvars} && !{path}_decr_sat{genvars})
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begin
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{path}_next{genvars} += {path}_incr_val{genvars};
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{path}_next{genvars} -= {path}_decr_val{genvars};
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{path}_next{genvars} += {{{incr_zero_pad}{path}_incr_val{genvars}}};
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{path}_next{genvars} -= {{{decr_zero_pad}{path}_decr_val{genvars}}};
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end
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end
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else if ({path}_incr{genvars})
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begin
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if (!{path}_incr_sat{genvars})
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<<INDENT>>
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{path}_next{genvars} += {path}_incr_val{genvars};
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{path}_next{genvars} += {{{incr_zero_pad}{path}_incr_val{genvars}}};
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<<UNINDENT>>
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end
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else if ({path}_decr{genvars})
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begin
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if (!{path}_decr_sat{genvars})
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<<INDENT>>
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{path}_next{genvars} += {path}_decr_val{genvars};
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{path}_next{genvars} -= {{{decr_zero_pad}{path}_decr_val{genvars}}};
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<<UNINDENT>>
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end
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end
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@ -359,7 +359,7 @@ counter_incr_sat:
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// Determine whether the counter is saturated
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// The signal is tied if the counter is not saturating
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// in the respective direction
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assign {path}_incr_sat{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {sat_value};
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assign {path}_incr_sat{genvars} = {{1'b0, {path}_q{genvars}}} + ({{{width_plus_1}{{{path}_incr}}}} & {{{incr_sat_zero_pad}{path}_incr_val}}) - ({{{width_plus_1}{{{path}_decr}}}} & {{{decr_sat_zero_pad}{path}_decr_val}}) > {{1'b0, {sat_value}}};
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signals:
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- name: '{path}_incr_sat'
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signal_type: 'logic'
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@ -375,7 +375,7 @@ counter_incr_sat_tied:
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signal_type: 'logic'
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counter_decr_sat:
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rtl: |-
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assign {path}_decr_sat{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {sat_value};
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assign {path}_decr_sat{genvars} = {{1'b0, {path}_q{genvars}}} + ({{{width_plus_1}{{{path}_incr}}}} & {{{incr_sat_zero_pad}{path}_incr_val}}) < {{1'b0, {sat_value}}} + ({{{width_plus_1}{{{path}_decr}}}} & {{{decr_sat_zero_pad}{path}_decr_val}});
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signals:
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- name: '{path}_decr_sat'
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signal_type: 'logic'
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@ -391,13 +391,13 @@ counter_thr_comment:
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// Define threshold signals (similar to overflow, but for a user specified value)
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counter_incr_thr:
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rtl: |-
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assign {path}_incr_thr{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {thr_value};
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assign {path}_incr_thr{genvars} = {{1'b0, {path}_q{genvars}}} + ({{{width_plus_1}{{{path}_incr}}}} & {{{incr_sat_zero_pad}{path}_incr_val}}) - ({{{width_plus_1}{{{path}_decr}}}} & {{{decr_sat_zero_pad}{path}_decr_val}}) >= {{1'b0, {thr_value}}};
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output_ports:
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- name: '{path}_incr_thr'
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signal_type: 'logic'
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counter_decr_thr:
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rtl: |-
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assign {path}_decr_thr{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {thr_value};
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assign {path}_decr_thr{genvars} = {{1'b0, {path}_q{genvars}}} + ({{{width_plus_1}{{{path}_incr}}}} & {{{incr_sat_zero_pad}{path}_incr_val}}) <= {{1'b0, {sat_value}}} + ({{{width_plus_1}{{{path}_decr}}}} & {{{decr_sat_zero_pad}{path}_decr_val}}) ;
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output_ports:
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- name: '{path}_decr_thr'
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signal_type: 'logic'
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@ -405,7 +405,7 @@ counter_overflow:
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rtl: |-
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// Logic to determine occurance of an overflow
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assign {path}_overflow_int{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {overflow_value};
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assign {path}_overflow_int{genvars} = {{1'b0, {path}_q{genvars}}} + ({{{width_plus_1}{{{path}_incr}}}} & {{{incr_sat_zero_pad}{path}_incr_val}}) - ({{{width_plus_1}{{{path}_decr}}}} & {{{decr_sat_zero_pad}{path}_decr_val}}) > {{1'b0, {overflow_value}}};
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assign {path}_overflow{genvars} = {path}_incr{genvars} && {path}_overflow_int{genvars};
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signals:
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- name: '{path}_overflow_int'
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@ -417,8 +417,8 @@ counter_underflow:
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rtl: |-
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// Logic to determine occurance of an underflow
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assign {path}_underflow_int{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {underflow_value};
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assign {path}_underflow{genvars} = {path}_incr{genvars} && {path}_underflow_int{genvars};
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assign {path}_underflow_int{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) > {underflow_value} + ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) ;
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assign {path}_underflow{genvars} = {path}_decr{genvars} && {path}_underflow_int{genvars};
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signals:
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- name: '{path}_underflow_int'
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signal_type: 'logic'
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