Gather bit-ranges of byte-enable signal in error-wire

Previously, the error wire would be assigned like this:

    assign example_reg_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])));

Now, this same line is simplified to:
    assign example_reg_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0])));

srdl2sv/components/register.py

@@ -215,11 +215,42 @@ class Register(Component):
             # an error.
             #
             # Furthermore, consider an error indication that is set for external registers
-            bytes_read_format = [f"widget_if.byte_en[{x}]" for x in list(map(str, bytes_read))]
+            wdgt_str = 'widget_if.byte_en'
-            bytes_written_format = [f"widget_if.byte_en[{x}]" for x in list(map(str, bytes_written))]
 
+            bytes_read_format = []
+            bytes_read_sorted = sorted(bytes_read, reverse = True)
+            prev = msb = bytes_read_sorted[0]
+
+            for i in bytes_read_sorted[1:]:
+                if prev - i > 1:
+                    bytes_read_format.append(
+                        f"|{wdgt_str}[{msb}:{prev}]" if msb > prev else f"{wdgt_str}[{msb}]")
+                    msb = i
+
+                if i == bytes_read_sorted[-1]:
+                    bytes_read_format.append(
+                        f"|{wdgt_str}[{msb}:{i}]" if msb > i else f"{wdgt_str}[{msb}]")
+
+                prev = i
+
+            bytes_written_format = []
+            bytes_written_sorted = sorted(bytes_written, reverse = True)
+            prev = msb = bytes_written_sorted[0]
+
+            for i in bytes_written_sorted[1:]:
+                if prev - i > 1:
+                    bytes_written_format.append(
+                        f"|{wdgt_str}[{msb}:{prev}]" if msb > prev else f"{wdgt_str}[{msb}]")
+                    msb = i
+
+                if i == bytes_written_sorted[-1]:
+                    bytes_written_format.append(
+                        f"|{wdgt_str}[{msb}:{i}]" if msb > i else f"{wdgt_str}[{msb}]")
+
+                prev = i
+
+            # Parse mux error-input
             sw_err_condition_vec = []
-
             sw_err_condition_vec.append(self._process_yaml(
                     Register.templ_dict['sw_err_condition'],
                     {'rd_byte_list_ored':