mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-12-22 06:58:41 +00:00
Closes #13: I/O ports are now grouped and are tied to the register the belong to
This commit is contained in:
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9d05c90d50
commit
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@ -153,81 +153,55 @@ class AddrMap(Component):
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for name in self.get_resets()
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for name in self.get_resets()
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]
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]
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ports_rtl = []
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# Prefetch dictionaries in local array
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# Prefetch dictionaries in local array
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input_dict_list = self.get_ports('input').items()
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port_dict_list = self.get_ports().items()
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output_dict_list = self.get_ports('output').items()
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input_signal_width = min(
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for group, ports in port_dict_list:
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max([len(value[0]) for (_, value) in input_dict_list]), 40)
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ports_rtl.append(f"// Ports for '{group}'")
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input_name_width = min(
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# Determine widths for this group
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max([len(key) for (key, _) in input_dict_list]), 40)
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signal_width = max(
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max([len(value.datatype) for (_, value) in ports.items()]), 12)
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output_signal_width = min(
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name_width = max([len(key) for (key, _) in ports.items()])
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max([len(value[0]) for (_, value) in output_dict_list]), 40)
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output_name_width = min(
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# Generate RTL
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max([len(key) for (key, _) in output_dict_list]), 40)
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for (key, port_type) in ports.items():
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# TODO: Think about a better way to handle datatypes. Simply replacing them
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# is not the most efficient way of handling it.
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signal_type = port_type.datatype.replace('logic', '').strip()
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if config['unpacked_arrays'] and port_type.dim:
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unpacked_dim = f"[{']['.join([str(y) for y in port_type.dim])}]"
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elif port_type.dim:
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unpacked_dim = ''
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signal_type = ''.join([
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f"[{':0]['.join([str(y-1) for y in port_type.dim])}:0]",
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signal_type
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])
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else:
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unpacked_dim = ''
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# Input ports
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ports_rtl.append(
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input_ports_rtl = []
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AddrMap.templ_dict['port']['rtl'].format(
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for (key, value) in input_dict_list:
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name = key,
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# TODO: Think about a better way to handle datatypes. Simply replacing them
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direction = port_type.direction,
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# is not the most efficient way of handling it.
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signal_type = signal_type,
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signal_type = value[0].replace('logic', '').strip()
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signal_width = signal_width,
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name_width = name_width,
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if config['unpacked_arrays'] and value[1]:
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unpacked_dim = unpacked_dim,
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unpacked_dim = f"[{']['.join([str(y) for y in value[1]])}]"
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)
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elif value[1]:
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unpacked_dim = ''
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signal_type = ''.join([
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f"[{':0]['.join([str(y-1) for y in value[1]])}:0]",
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signal_type
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])
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else:
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unpacked_dim = ''
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input_ports_rtl.append(
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AddrMap.templ_dict['input_port']['rtl'].format(
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name = key,
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signal_type = signal_type,
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signal_width = input_signal_width,
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name_width = input_name_width,
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unpacked_dim = unpacked_dim,
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)
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)
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)
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# Output ports
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# Append a new line after every port
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output_ports_rtl = []
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ports_rtl.append('')
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for (key, value) in output_dict_list:
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# TODO: Think about a better way to handle datatypes. Simply replacing them
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# is not the most efficient way of handling it.
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signal_type = value[0].replace('logic', '').strip()
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if config['unpacked_arrays'] and value[1]:
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unpacked_dim = f"[{']['.join([str(y) for y in value[1]])}]"
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elif value[1]:
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unpacked_dim = ''
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signal_type = ''.join([
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f"[{':0]['.join([str(y-1) for y in value[1]])}:0]",
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signal_type
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])
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else:
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unpacked_dim = ''
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output_ports_rtl.append(
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AddrMap.templ_dict['output_port']['rtl'].format(
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name = key,
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signal_type = signal_type,
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signal_width = output_signal_width,
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name_width = output_name_width,
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unpacked_dim = unpacked_dim,
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)
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)
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# Remove last newline
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# Remove comma from last port entry
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# Remove comma from last port entry
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output_ports_rtl[-1] = output_ports_rtl[-1].rstrip(',')
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ports_rtl.pop()
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ports_rtl[-1] = ports_rtl[-1].rstrip(',')
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# Define packages to be included. Always include the
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# Define packages to be included. Always include the
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# b2w and w2b defines.
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# b2w and w2b defines.
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@ -268,8 +242,7 @@ class AddrMap(Component):
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name = self.name,
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name = self.name,
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import_package_list = ''.join(import_package_list),
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import_package_list = ''.join(import_package_list),
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resets = '\n'.join(reset_ports_rtl),
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resets = '\n'.join(reset_ports_rtl),
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inputs = '\n'.join(input_ports_rtl),
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ports = '\n'.join(ports_rtl)))
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outputs = '\n'.join(output_ports_rtl)))
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# Add description, if applicable
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# Add description, if applicable
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self.rtl_header.append(self.get_description())
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self.rtl_header.append(self.get_description())
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@ -321,8 +294,8 @@ class AddrMap(Component):
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def __add_signal_instantiation(self):
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def __add_signal_instantiation(self):
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dict_list = list(self.get_signals(True).items())
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dict_list = list(self.get_signals(True).items())
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signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)
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signal_width = max(max([len(value.datatype) for (_, value) in dict_list]), 12)
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name_width = min(max([len(key) for (key, _) in dict_list]), 40)
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name_width = max([len(key) for (key, _) in dict_list])
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self.rtl_header = [
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self.rtl_header = [
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*self.rtl_header,
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*self.rtl_header,
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@ -330,13 +303,13 @@ class AddrMap(Component):
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'// Internal signals',
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'// Internal signals',
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*[AddrMap.templ_dict['signal_declaration'].format(
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*[AddrMap.templ_dict['signal_declaration'].format(
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name = key,
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name = key,
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type = value[0],
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type = value.datatype,
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signal_width = signal_width,
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signal_width = signal_width,
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name_width = name_width,
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name_width = name_width,
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unpacked_dim = '[{}]'.format(
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unpacked_dim = '[{}]'.format(
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']['.join(
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']['.join(
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[str(y) for y in value[1]]))
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[str(y) for y in value.dim]))
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if value[1] else '')
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if value.dim else '')
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for (key, value) in dict_list],
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for (key, value) in dict_list],
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''
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''
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]
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]
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@ -3,6 +3,7 @@ import math
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import sys
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import sys
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from typing import NamedTuple, Optional
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from typing import NamedTuple, Optional
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from dataclasses import dataclass
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from dataclasses import dataclass
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from enum import Enum
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from systemrdl import node
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from systemrdl import node
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@ -27,6 +28,15 @@ class SWMuxEntryDimensioned():
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mux_entry: SWMuxEntry
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mux_entry: SWMuxEntry
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dim: str
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dim: str
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class SignalType(NamedTuple):
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datatype: str
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dim: list
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class PortType(NamedTuple):
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datatype: str
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dim: list
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direction: str # String "input" or "output"
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class Component():
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class Component():
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def __init__(
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def __init__(
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self,
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self,
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@ -42,8 +52,6 @@ class Component():
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self.ports = {}
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self.ports = {}
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self.resets = set()
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self.resets = set()
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self.signals = {}
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self.signals = {}
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self.ports['input'] = {}
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self.ports['output'] = {}
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self.field_type = ''
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self.field_type = ''
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# Save object
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# Save object
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@ -146,13 +154,19 @@ class Component():
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return self.resets
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return self.resets
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def get_ports(self, port_type: str):
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def get_ports(self):
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self.logger.debug("Return port list")
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self.logger.debug("Return port list")
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for child in self.children.values():
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for child in self.children.values():
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self.ports[port_type] |= child.get_ports(port_type)
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for key, value in child.get_ports().items():
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if key in self.ports:
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self.logger.debug("Group '%s' already present in port list")
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self.ports[key] |= value
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else:
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self.logger.debug("Adding group '%s' to port list")
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self.ports |= {key: value}
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return self.ports[port_type]
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return self.ports
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def get_max_dim_depth(self) -> int:
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def get_max_dim_depth(self) -> int:
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self.logger.debug("Return depth '%s' for dimensions (including parents) '%s'.",
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self.logger.debug("Return depth '%s' for dimensions (including parents) '%s'.",
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@ -285,8 +299,12 @@ class Component():
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name.append('_q')
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name.append('_q')
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elif isinstance(obj, node.SignalNode):
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elif isinstance(obj, node.SignalNode):
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# Must add it to signal list
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# Must add it to signal list
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self.ports['input'][obj.inst_name] =\
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self.ports['Signals'][obj.inst_name] =\
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("logic" if obj.width == 1 else f"logic [{obj.width}:0]", [])
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PortType (
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datatype = "logic" if obj.width == 1 else f"logic [{obj.width}:0]",
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dim = [],
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direction = "input"
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)
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else:
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else:
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name.append('_')
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name.append('_')
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name.append(obj.name)
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name.append(obj.name)
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@ -325,8 +343,10 @@ class Component():
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array_dimensions = self.total_array_dimensions
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array_dimensions = self.total_array_dimensions
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self.signals[signal['name'].format(**values)] =\
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self.signals[signal['name'].format(**values)] =\
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(signal['signal_type'].format(**values),
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SignalType (
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array_dimensions)
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datatype = signal['signal_type'].format(**values),
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dim = array_dimensions,
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)
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except (TypeError, KeyError):
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except (TypeError, KeyError):
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pass
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pass
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@ -341,9 +361,29 @@ class Component():
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except KeyError:
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except KeyError:
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array_dimensions = self.total_array_dimensions
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array_dimensions = self.total_array_dimensions
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self.ports['input'][input_p['name'].format(**values)] =\
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try:
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(input_p['signal_type'].format(**values),
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group = input_p['group'].format(**values)
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array_dimensions)
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except KeyError:
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group = self.path_underscored_wo_field
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name = input_p['name'].format(**values)
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if group not in self.ports:
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self.ports[group] = {
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name:
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PortType (
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datatype = input_p['signal_type'].format(**values),
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dim = array_dimensions,
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direction = "input",
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)
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}
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elif name not in self.ports[group]:
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self.ports[group][name] =\
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PortType (
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datatype = input_p['signal_type'].format(**values),
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dim = array_dimensions,
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direction = "input",
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)
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except (TypeError, KeyError):
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except (TypeError, KeyError):
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pass
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pass
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@ -358,9 +398,29 @@ class Component():
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except KeyError:
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except KeyError:
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array_dimensions = self.total_array_dimensions
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array_dimensions = self.total_array_dimensions
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self.ports['output'][output_p['name'].format(**values)] =\
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try:
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(output_p['signal_type'].format(**values),
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group = output_p['group'].format(**values)
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array_dimensions)
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except KeyError:
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group = self.path_underscored_wo_field
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name = output_p['name'].format(**values)
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if group not in self.ports:
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self.ports[group] = {
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name:
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PortType (
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datatype = output_p['signal_type'].format(**values),
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dim = array_dimensions,
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direction = "output",
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)
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}
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elif name not in self.ports[group]:
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self.ports[group][name] =\
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PortType (
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datatype = output_p['signal_type'].format(**values),
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dim = array_dimensions,
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direction = "output",
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)
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except (TypeError, KeyError):
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except (TypeError, KeyError):
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pass
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pass
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@ -371,6 +431,9 @@ class Component():
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self.owning_addrmap, self.full_path, self.path, self.path_underscored =\
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self.owning_addrmap, self.full_path, self.path, self.path_underscored =\
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Component.create_underscored_path_static(self.obj)
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Component.create_underscored_path_static(self.obj)
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# By default, this is identical to path_underscored. Fields will override this
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self.path_underscored_wo_field = self.path_underscored
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@staticmethod
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@staticmethod
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def create_underscored_path_static(obj):
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def create_underscored_path_static(obj):
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owning_addrmap = obj.owning_addrmap.inst_name
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owning_addrmap = obj.owning_addrmap.inst_name
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@ -110,10 +110,11 @@ class Field(Component):
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else:
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else:
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path = self.path
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path = self.path
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path_wo_field = '__'.join(path.split('.', -1)[0:-1])
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# This is different than self.path_underscored_wo_field
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path_underscored_wo_field = '__'.join(path.split('.', -1)[0:-1])
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# path_wo_field_vec & path_undrescored_vec only used for external registers
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# path_wo_field_vec & path_undrescored_vec only used for external registers
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self.path_wo_field_vec.append(path_wo_field)
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self.path_wo_field_vec.append(path_underscored_wo_field)
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self.path_underscored_vec.append(alias_path_underscored if alias else self.path_underscored)
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self.path_underscored_vec.append(alias_path_underscored if alias else self.path_underscored)
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# Define software access (if applicable)
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# Define software access (if applicable)
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@ -121,7 +122,7 @@ class Field(Component):
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if self.properties['sw_wr']:
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if self.properties['sw_wr']:
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# Append to list of registers that can write
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# Append to list of registers that can write
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self.writable_by.add(path_wo_field)
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self.writable_by.add(path_underscored_wo_field)
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# This will need a wire to indicate that a write is taking place
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# This will need a wire to indicate that a write is taking place
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self.properties['sw_wr_wire'] = True
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self.properties['sw_wr_wire'] = True
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@ -133,7 +134,7 @@ class Field(Component):
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access_rtl['sw_write'][0].append(
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access_rtl['sw_write'][0].append(
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self._process_yaml(
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self._process_yaml(
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Field.templ_dict['sw_access_field_swwe'],
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Field.templ_dict['sw_access_field_swwe'],
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{'path_wo_field': path_wo_field,
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{'path_wo_field': path_underscored_wo_field,
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'genvars': self.genvars_str,
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'genvars': self.genvars_str,
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'swwe': self.get_signal_name(swwe),
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'swwe': self.get_signal_name(swwe),
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'field_type': self.field_type}
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'field_type': self.field_type}
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@ -143,7 +144,7 @@ class Field(Component):
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access_rtl['sw_write'][0].append(
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access_rtl['sw_write'][0].append(
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self._process_yaml(
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self._process_yaml(
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Field.templ_dict['sw_access_field_swwel'],
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Field.templ_dict['sw_access_field_swwel'],
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{'path_wo_field': path_wo_field,
|
{'path_wo_field': path_underscored_wo_field,
|
||||||
'genvars': self.genvars_str,
|
'genvars': self.genvars_str,
|
||||||
'swwel': self.get_signal_name(swwel),
|
'swwel': self.get_signal_name(swwel),
|
||||||
'field_type': self.field_type}
|
'field_type': self.field_type}
|
||||||
@ -153,7 +154,7 @@ class Field(Component):
|
|||||||
access_rtl['sw_write'][0].append(
|
access_rtl['sw_write'][0].append(
|
||||||
self._process_yaml(
|
self._process_yaml(
|
||||||
Field.templ_dict['sw_access_field'],
|
Field.templ_dict['sw_access_field'],
|
||||||
{'path_wo_field': path_wo_field,
|
{'path_wo_field': path_underscored_wo_field,
|
||||||
'genvars': self.genvars_str,
|
'genvars': self.genvars_str,
|
||||||
'field_type': self.field_type}
|
'field_type': self.field_type}
|
||||||
)
|
)
|
||||||
@ -211,7 +212,7 @@ class Field(Component):
|
|||||||
|
|
||||||
if obj.get_property('sw') in (AccessType.rw, AccessType.r):
|
if obj.get_property('sw') in (AccessType.rw, AccessType.r):
|
||||||
# Append to list of registers that can read
|
# Append to list of registers that can read
|
||||||
self.readable_by.add(path_wo_field)
|
self.readable_by.add(path_underscored_wo_field)
|
||||||
|
|
||||||
self.properties['sw_rd'] = True
|
self.properties['sw_rd'] = True
|
||||||
|
|
||||||
@ -224,7 +225,7 @@ class Field(Component):
|
|||||||
access_rtl['sw_read'][0].append(
|
access_rtl['sw_read'][0].append(
|
||||||
self._process_yaml(
|
self._process_yaml(
|
||||||
Field.templ_dict['sw_read_access_field'],
|
Field.templ_dict['sw_read_access_field'],
|
||||||
{'path_wo_field': path_wo_field,
|
{'path_wo_field': path_underscored_wo_field,
|
||||||
'genvars': self.genvars_str,
|
'genvars': self.genvars_str,
|
||||||
'field_type': self.field_type}
|
'field_type': self.field_type}
|
||||||
)
|
)
|
||||||
@ -711,7 +712,7 @@ class Field(Component):
|
|||||||
self._process_yaml(
|
self._process_yaml(
|
||||||
Field.templ_dict['swmod_assign'],
|
Field.templ_dict['swmod_assign'],
|
||||||
{'path': self.path_underscored,
|
{'path': self.path_underscored,
|
||||||
'path_wo_field': self.path_wo_field,
|
'path_wo_field': self.path_underscored_wo_field,
|
||||||
'genvars': self.genvars_str,
|
'genvars': self.genvars_str,
|
||||||
'rd_wr': 'rd',
|
'rd_wr': 'rd',
|
||||||
'msbyte': self.msbyte,
|
'msbyte': self.msbyte,
|
||||||
@ -727,7 +728,7 @@ class Field(Component):
|
|||||||
self._process_yaml(
|
self._process_yaml(
|
||||||
Field.templ_dict['swmod_assign'],
|
Field.templ_dict['swmod_assign'],
|
||||||
{'path': self.path_underscored,
|
{'path': self.path_underscored,
|
||||||
'path_wo_field': self.path_wo_field,
|
'path_wo_field': self.path_underscored_wo_field,
|
||||||
'genvars': self.genvars_str,
|
'genvars': self.genvars_str,
|
||||||
'rd_wr': 'wr',
|
'rd_wr': 'wr',
|
||||||
'msbyte': self.msbyte,
|
'msbyte': self.msbyte,
|
||||||
@ -762,7 +763,7 @@ class Field(Component):
|
|||||||
swacc_props = self._process_yaml(
|
swacc_props = self._process_yaml(
|
||||||
Field.templ_dict['swacc_assign'],
|
Field.templ_dict['swacc_assign'],
|
||||||
{'path': self.path_underscored,
|
{'path': self.path_underscored,
|
||||||
'path_wo_field': self.path_wo_field,
|
'path_wo_field': self.path_underscored_wo_field,
|
||||||
'genvars': self.genvars_str,
|
'genvars': self.genvars_str,
|
||||||
'msbyte': self.msbyte,
|
'msbyte': self.msbyte,
|
||||||
'lsbyte': self.lsbyte,
|
'lsbyte': self.lsbyte,
|
||||||
@ -1349,7 +1350,7 @@ class Field(Component):
|
|||||||
self,
|
self,
|
||||||
obj: FieldNode):
|
obj: FieldNode):
|
||||||
# Create full name
|
# Create full name
|
||||||
self.path_wo_field = '__'.join(self.path.split('.', -1)[0:-1])
|
self.path_underscored_wo_field = '__'.join(self.path.split('.', -1)[0:-1])
|
||||||
self.register_name = ''.join([self.path_underscored, '_q'])
|
self.register_name = ''.join([self.path_underscored, '_q'])
|
||||||
|
|
||||||
self.path_underscored_vec = []
|
self.path_underscored_vec = []
|
||||||
@ -1451,7 +1452,7 @@ class Field(Component):
|
|||||||
external = self.config['external'],
|
external = self.config['external'],
|
||||||
lsb = self.obj.lsb,
|
lsb = self.obj.lsb,
|
||||||
msb = self.obj.msb,
|
msb = self.obj.msb,
|
||||||
path_wo_field = self.path_wo_field,
|
path_wo_field = self.path_underscored_wo_field,
|
||||||
storage_type = self.storage_type,
|
storage_type = self.storage_type,
|
||||||
)
|
)
|
||||||
|
|
||||||
|
@ -511,20 +511,18 @@ class Register(Component):
|
|||||||
|
|
||||||
def get_signal_instantiations_list(self):
|
def get_signal_instantiations_list(self):
|
||||||
dict_list = list(self.get_signals().items())
|
dict_list = list(self.get_signals().items())
|
||||||
|
signal_width = max(max([len(value.datatype) for (_, value) in dict_list]), 12)
|
||||||
signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)
|
name_width = max([len(key) for (key, _) in dict_list])
|
||||||
|
|
||||||
name_width = min(max([len(key) for (key, _) in dict_list]), 40)
|
|
||||||
|
|
||||||
return [Register.templ_dict['signal_declaration'].format(
|
return [Register.templ_dict['signal_declaration'].format(
|
||||||
name = key,
|
name = key,
|
||||||
type = value[0],
|
type = value.datatype,
|
||||||
signal_width = signal_width,
|
signal_width = signal_width,
|
||||||
name_width = name_width,
|
name_width = name_width,
|
||||||
unpacked_dim = '[{}]'.format(
|
unpacked_dim = '[{}]'.format(
|
||||||
']['.join(
|
']['.join(
|
||||||
[str(y) for y in value[1]]))
|
[str(y) for y in value.dim]))
|
||||||
if value[1] else '')
|
if value.dim else '')
|
||||||
for (key, value) in dict_list]
|
for (key, value) in dict_list]
|
||||||
|
|
||||||
def add_alias(self, obj: node.RegNode):
|
def add_alias(self, obj: node.RegNode):
|
||||||
|
@ -75,14 +75,11 @@ module_declaration:
|
|||||||
<<UNINDENT>>
|
<<UNINDENT>>
|
||||||
(
|
(
|
||||||
<<INDENT>>
|
<<INDENT>>
|
||||||
// Resets
|
// Reset signals declared for registers
|
||||||
{resets}
|
{resets}
|
||||||
|
|
||||||
// Inputs
|
{ports}
|
||||||
{inputs}
|
|
||||||
|
|
||||||
// Outputs
|
|
||||||
{outputs}
|
|
||||||
<<UNINDENT>>
|
<<UNINDENT>>
|
||||||
);
|
);
|
||||||
import_package:
|
import_package:
|
||||||
@ -91,12 +88,9 @@ import_package:
|
|||||||
reset_port:
|
reset_port:
|
||||||
rtl:
|
rtl:
|
||||||
input {name},
|
input {name},
|
||||||
input_port:
|
port:
|
||||||
rtl:
|
rtl: |-
|
||||||
input {signal_type:{signal_width}} {name:{name_width}}{unpacked_dim},
|
{direction:6} {signal_type:{signal_width}} {name:{name_width}}{unpacked_dim},
|
||||||
output_port:
|
|
||||||
rtl:
|
|
||||||
output {signal_type:{signal_width}} {name:{name_width}}{unpacked_dim},
|
|
||||||
signal_declaration: |-
|
signal_declaration: |-
|
||||||
{type:{signal_width}} {name:{name_width}}{unpacked_dim};
|
{type:{signal_width}} {name:{name_width}}{unpacked_dim};
|
||||||
package_declaration:
|
package_declaration:
|
||||||
|
@ -40,26 +40,38 @@ module_instantiation:
|
|||||||
input_ports:
|
input_ports:
|
||||||
- name: 'clk'
|
- name: 'clk'
|
||||||
signal_type: ''
|
signal_type: ''
|
||||||
|
group: 'General Clock'
|
||||||
- name: 'HRESETn'
|
- name: 'HRESETn'
|
||||||
signal_type: ''
|
signal_type: ''
|
||||||
|
group: 'AHB Protocol'
|
||||||
- name: 'HADDR'
|
- name: 'HADDR'
|
||||||
signal_type: '[31:0]'
|
signal_type: '[31:0]'
|
||||||
|
group: 'AHB Protocol'
|
||||||
- name: 'HWRITE'
|
- name: 'HWRITE'
|
||||||
signal_type: ''
|
signal_type: ''
|
||||||
|
group: 'AHB Protocol'
|
||||||
- name: 'HSIZE'
|
- name: 'HSIZE'
|
||||||
signal_type: '[2:0]'
|
signal_type: '[2:0]'
|
||||||
|
group: 'AHB Protocol'
|
||||||
- name: 'HPROT'
|
- name: 'HPROT'
|
||||||
signal_type: '[3:0]'
|
signal_type: '[3:0]'
|
||||||
|
group: 'AHB Protocol'
|
||||||
- name: 'HTRANS'
|
- name: 'HTRANS'
|
||||||
signal_type: '[1:0]'
|
signal_type: '[1:0]'
|
||||||
|
group: 'AHB Protocol'
|
||||||
- name: 'HWDATA'
|
- name: 'HWDATA'
|
||||||
signal_type: '[{bus_width}-1:0]'
|
signal_type: '[{bus_width}-1:0]'
|
||||||
|
group: 'AHB Protocol'
|
||||||
- name: 'HSEL'
|
- name: 'HSEL'
|
||||||
signal_type: ''
|
signal_type: ''
|
||||||
|
group: 'AHB Protocol'
|
||||||
output_ports:
|
output_ports:
|
||||||
- name: 'HREADYOUT'
|
- name: 'HREADYOUT'
|
||||||
signal_type: ''
|
signal_type: ''
|
||||||
|
group: 'AHB Protocol'
|
||||||
- name: 'HRESP'
|
- name: 'HRESP'
|
||||||
signal_type: ''
|
signal_type: ''
|
||||||
|
group: 'AHB Protocol'
|
||||||
- name: 'HRDATA'
|
- name: 'HRDATA'
|
||||||
signal_type: '[{bus_width}-1:0]'
|
signal_type: '[{bus_width}-1:0]'
|
||||||
|
group: 'AHB Protocol'
|
||||||
|
Loading…
Reference in New Issue
Block a user