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Add bus_clk/bus_rst_n ports to widget (rather than (only) reg_clk)

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This commit is contained in:
Dennis Potter 2021-06-25 11:50:06 +02:00
parent 6565c33445
commit baf08d2343
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
3 changed files with 8 additions and 3 deletions
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3
srdl2sv/components/widgets/amba3ahblite.sv
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@ -1,7 +1,8 @@
module amba3ahblite_widget module amba3ahblite_widget
( (
// Register clock // Register clock
input reg_clk, input bus_clk,
input bus_rst_n,
// Outputs to internal logic // Outputs to internal logic
output [31:0] addr, output [31:0] addr,

5
srdl2sv/components/widgets/amba3ahblite.yaml
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@ -6,8 +6,9 @@ module_instantiation:
****************************/ ****************************/
amba3ahblite_widget amba3ahblite_widget
amba3ahblite_widget_inst amba3ahblite_widget_inst
(// Register clock (// Clocks & Resets
.reg_clk, .bus_clk,
.bus_rst_n,
// Outputs to internal logic // Outputs to internal logic
.addr, .addr,

3
srdl2sv/main.py
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@ -85,4 +85,7 @@ if __name__ == "__main__":
with open(out_widget_file, 'w') as file: with open(out_widget_file, 'w') as file:
file.write(widget_rtl) file.write(widget_rtl)
logger.info("Selected, implemented, and copied '{}' widget".format(config['bus']))
# Print elapsed time
logger.info("Elapsed time: %f seconds", time.time() - start) logger.info("Elapsed time: %f seconds", time.time() - start)