Add bus_clk/bus_rst_n ports to widget (rather than (only) reg_clk)

srdl2sv/components/widgets/amba3ahblite.sv

@@ -1,7 +1,8 @@
 module amba3ahblite_widget
 (
     // Register clock
-    input         reg_clk,
+    input         bus_clk,
+    input         bus_rst_n,
 
     // Outputs to internal logic
     output [31:0] addr,

srdl2sv/components/widgets/amba3ahblite.yaml

@@ -6,8 +6,9 @@ module_instantiation:
          ****************************/
         amba3ahblite_widget
         amba3ahblite_widget_inst
-            (// Register clock
-             .reg_clk,
+            (// Clocks & Resets
+             .bus_clk,
+             .bus_rst_n,
 
              // Outputs to internal logic
              .addr,

srdl2sv/main.py

@@ -85,4 +85,7 @@ if __name__ == "__main__":
     with open(out_widget_file, 'w') as file:
         file.write(widget_rtl)
 
+    logger.info("Selected, implemented, and copied '{}' widget".format(config['bus']))
+
+    # Print elapsed time
     logger.info("Elapsed time: %f seconds", time.time() - start)