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Change way SV keyword 'else' is added to access_rtl

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At this point, it is still added in an for-loop. The reason is that
this code might get more extensive and become otherwise unreadable.
This commit is contained in:
Dennis Potter 2021-05-08 11:52:34 +02:00
parent ea998b7db0
commit c32bfdd8c0
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
1 changed files with 21 additions and 8 deletions
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29
srdl2sv/components/field.py
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@ -130,6 +130,10 @@ class Field:
field_name = obj.inst_name, field_name = obj.inst_name,
genvars = genvars_str, genvars = genvars_str,
indent = self.indent(indent_lvl))) indent = self.indent(indent_lvl)))
else:
access_rtl['hw_write'].append(
Field.templ_dict['hw_access_no_we_wel'].format(
indent = self.indent(indent_lvl)))
access_rtl['hw_write'].append( access_rtl['hw_write'].append(
Field.templ_dict['hw_access_field'].format( Field.templ_dict['hw_access_field'].format(
@ -173,18 +177,27 @@ class Field:
# Check if hardware has precedence (default `precedence = sw`) # Check if hardware has precedence (default `precedence = sw`)
if precedence == 'PrecedenceType.sw': if precedence == 'PrecedenceType.sw':
rtl_order = ['sw_write', order_list = ['sw_write',
'else' if len(access_rtl['hw_write']) > 0 else '',
'hw_write'] 'hw_write']
else: else:
rtl_order = ['hw_write', order_list = ['hw_write',
'else' if len(access_rtl['sw_write']) > 0 else '',
'sw_write'] 'sw_write']
# Add dictionary to main RTL list in correct order # Add appropriate else
self.rtl = [ order_list_rtl = []
*self.rtl,
*chain.from_iterable([access_rtl[i] for i in rtl_order])] for i in order_list:
# Still a loop and not a list comprehension since this might
# get longer in the future and thus become unreadable
if len(access_rtl[i]) > 0:
order_list_rtl = [*order_list_rtl, *access_rtl[i]]
order_list_rtl.append("{}else".format(self.indent(indent_lvl)))
# Remove last pop
order_list_rtl.pop()
# Chain access RTL to the rest of the RTL
self.rtl = [*self.rtl, *order_list_rtl]
indent_lvl -= 1 indent_lvl -= 1