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A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
4 Commits 1 Branch 0 Tags 713 KiB
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%
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Dennis c32bfdd8c0
Change way SV keyword 'else' is added to access_rtl 
At this point, it is still added in an for-loop. The reason is that
this code might get more extensive and become otherwise unreadable.
2021-05-08 11:52:34 +02:00
srdl2sv Change way SV keyword 'else' is added to access_rtl 2021-05-08 11:52:34 +02:00
.gitignore Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00
LIMITATIONS.md Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00