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Removed genvars in case only 1 dimension with 1 entry is used

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This commit is contained in:
Dennis Potter 2021-05-17 00:15:43 +02:00
parent 203f1e1b36
commit c5755bf104
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
5 changed files with 22 additions and 14 deletions
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12
srdl2sv/components/addrmap.py
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@ -8,7 +8,6 @@ from systemrdl.node import FieldNode
# Local packages # Local packages
from components.component import Component from components.component import Component
from components.register import Register from components.register import Register
from log.log import create_logger
from . import templates from . import templates
@ -64,14 +63,21 @@ class AddrMap(Component):
AddrMap.templ_dict['input_port'].format( AddrMap.templ_dict['input_port'].format(
name = x.name, name = x.name,
packed_dim = x.packed_dim, packed_dim = x.packed_dim,
unpacked_dim = '[{}]'.format(']['.join([str(y) for y in x.unpacked_dim]))) unpacked_dim = '[{}]'.format(
']['.join(
[str(y) for y in x.unpacked_dim]))
if x.unpacked_dim else '')
for x in self.get_ports('input')] for x in self.get_ports('input')]
# Output ports # Output ports
output_ports_rtl = [ output_ports_rtl = [
AddrMap.templ_dict['output_port'].format( AddrMap.templ_dict['output_port'].format(
name = x.name, name = x.name,
packed_dim = x.packed_dim, packed_dim = x.packed_dim,
unpacked_dim = '[{}]'.format(']['.join([str(y) for y in x.unpacked_dim]))) unpacked_dim = '[{}]'.format(
']['.join(
[str(y) for y in x.unpacked_dim]))
if x.unpacked_dim else '')
for x in self.get_ports('output')] for x in self.get_ports('output')]
# Remove comma from last port entry # Remove comma from last port entry

6
srdl2sv/components/component.py
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@ -124,9 +124,3 @@ class Component():
name.append(split_name[1]) name.append(split_name[1])
return ''.join(name) return ''.join(name)

11
srdl2sv/components/register.py
View File

@ -66,13 +66,18 @@ class Register(Component):
# Assign variables from bus # Assign variables from bus
self.obj.current_idx = [0] self.obj.current_idx = [0]
if self.dimensions:
rw_wire_assign_field = 'rw_wire_assign_multi_dim'
else:
rw_wire_assign_field = 'rw_wire_assign_1_dim'
self.rtl_header.append( self.rtl_header.append(
Register.templ_dict['rw_wire_assign'].format( Register.templ_dict[rw_wire_assign_field].format(
path = self.path, path = self.path,
addr = self.obj.absolute_address, addr = self.obj.absolute_address,
genvars = self.genvars_str, genvars = self.genvars_str,
genvars_sum =self.genvars_sum_str, genvars_sum =self.genvars_sum_str,
stride = self.obj.array_stride if self.obj.array_stride else '0', stride = self.obj.array_stride,
depth = self.depth)) depth = self.depth))
def __process_variables(self, obj: node.RootNode): def __process_variables(self, obj: node.RootNode):
@ -96,7 +101,7 @@ class Register(Component):
self.array_dimensions = self.obj.array_dimensions self.array_dimensions = self.obj.array_dimensions
else: else:
self.sel_arr = 'single' self.sel_arr = 'single'
self.array_dimensions = [1] self.array_dimensions = []
self.depth = '[{}]'.format(']['.join(f"{i}" for i in self.array_dimensions)) self.depth = '[{}]'.format(']['.join(f"{i}" for i in self.array_dimensions))
self.dimensions = len(self.array_dimensions) self.dimensions = len(self.array_dimensions)

2
srdl2sv/components/templates/fields.yaml
View File

@ -95,5 +95,5 @@ singlepulse: |-
out_port_assign: |- out_port_assign: |-
// Connect register to hardware output port // Connect register to hardware output port
assign {path}_r{genvars} <= {path}_q{genvars}; assign {path}_r{genvars} = {path}_q{genvars};

5
srdl2sv/components/templates/regs.yaml
View File

@ -2,7 +2,10 @@
rw_wire_declare: | rw_wire_declare: |
logic {path}_sw_wr {depth}; logic {path}_sw_wr {depth};
logic {path}_sw_rd {depth}; logic {path}_sw_rd {depth};
rw_wire_assign: | rw_wire_assign_1_dim: |
assign {path}_sw_wr{genvars} = addr == {addr} && r_vld;
assign {path}_sw_rd{genvars} = addr == {addr} && w_vld;
rw_wire_assign_multi_dim: |
assign {path}_sw_wr{genvars} = addr == ({addr}+({genvars_sum})*{stride}) && r_vld; assign {path}_sw_wr{genvars} = addr == ({addr}+({genvars_sum})*{stride}) && r_vld;
assign {path}_sw_rd{genvars} = addr == ({addr}+({genvars_sum})*{stride}) && w_vld; assign {path}_sw_rd{genvars} = addr == ({addr}+({genvars_sum})*{stride}) && w_vld;
reg_comment: |- reg_comment: |-