Add proper support for rdy & error indication in read multiplexer
The error indication is generated if:
- A non-existent register gets read
- An existent register gets read but not a single bit can be
succesfully read or written. As soon as 1 bit succeeds don't
return an error.
This commit is contained in:
parent
2f38d30d76
commit
c689190080
GPG Key ID:
186A8AD440942BAF
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@ -194,21 +194,39 @@ class AddrMap(Component):
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def __create_mux_string(self):
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# TODO: Add variable for bus width
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# Define default case
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list_of_cases = [AddrMap.templ_dict['default_mux_case']['rtl']]
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# Add an entry for each version of a register
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for child in self.children.values():
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for mux_entry in child.create_mux_string():
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# Data structure of mux_entry:
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# mux_entry[0] --> names of data/rdy/err wire and start addr
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# [0] --> data_mux (str)
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# [1] --> rdy_mux (str)
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# [2] --> err_mux (str)
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# [3] --> start_addr (int)
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# mux_entry[1] --> offsets from start
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# [0] --> Offset from start_addr of current entry (int)
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# [1] --> String of array index that represents offset (str)
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r2b_data = ''.join([mux_entry[0][0], mux_entry[1][1]])
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r2b_rdy = ''.join([mux_entry[0][1], mux_entry[1][1]])
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r2b_err = ''.join([mux_entry[0][2], mux_entry[1][1]])
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index = mux_entry[0][3] + mux_entry[1][0]
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list_of_cases.append(
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AddrMap.templ_dict['list_of_mux_cases']['rtl'].format(
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index = index,
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r2b_data = r2b_data,
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r2b_rdy = r2b_rdy,
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r2b_err = r2b_err)
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)
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self.rtl_footer.append(
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self.process_yaml(
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AddrMap.templ_dict['read_mux'],
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{'list_of_cases':
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'\n'.join([
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AddrMap.templ_dict['default_mux_case']['rtl'],
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*[AddrMap.templ_dict['list_of_mux_cases']['rtl']
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.format(x[0][1]+x[1][0],
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''.join(
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[x[0][0],
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x[1][1]])) for y in self.children.values() \
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for x in y.create_mux_string()
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]
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])
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}
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{'list_of_cases': '\n'.join(list_of_cases)}
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)
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)
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@ -68,6 +68,9 @@ class Field(Component):
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access_rtl['sw_write'] = ([], False)
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if obj.get_property('sw') in (AccessType.rw, AccessType.w):
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# Append to list of registers that can write
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self.writable_by.add(path_wo_field)
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swwe = obj.get_property('swwe')
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swwel = obj.get_property('swwel')
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@ -1005,8 +1008,9 @@ class Field(Component):
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self.msb = obj.inst.msb
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self.lsb = obj.inst.lsb
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# Set that tells which hierarchies can read this field
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# Set that tells which hierarchies can read/write this field
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self.readable_by = set()
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self.writable_by = set()
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# Determine resets. This includes checking for async/sync resets,
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# the reset value, and whether the field actually has a reset
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@ -73,7 +73,7 @@ class Register(Component):
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self.rtl_footer.append("endgenerate\n")
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# Add assignment of read-wires
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self.__add_sw_read_assignments()
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self.__add_sw_mux_assignments()
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# Add wire instantiation
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if not self.generate_active:
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@ -90,22 +90,36 @@ class Register(Component):
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*self.rtl_header
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]
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def __add_sw_read_assignments(self):
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def __add_sw_mux_assignments(self):
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accesswidth = self.obj.get_property('accesswidth') - 1
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self.rtl_footer.append("")
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for x in self.name_addr_mappings:
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for na_map in self.name_addr_mappings:
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current_bit = 0
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# Start tracking errors
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# Handle fields
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list_of_fields = []
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for y in self.children.values():
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if x[0] in y.readable_by:
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empty_bits = y.lsb - current_bit
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current_bit = y.msb + 1
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bytes_read = set()
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bytes_written = set()
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for field in self.children.values():
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if na_map[0] in field.readable_by:
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empty_bits = field.lsb - current_bit
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current_bit = field.msb + 1
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if empty_bits > 0:
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list_of_fields.append("{}'b0".format(empty_bits))
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list_of_fields.append("{}_q".format(y.path_underscored))
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list_of_fields.append("{}_q".format(field.path_underscored))
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# Add to appropriate bytes
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[bytes_read.add(x) for x in range(field.lsbyte, field.msbyte+1)]
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if na_map[0] in field.writable_by:
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# Add to appropriate bytes
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[bytes_written.add(x) for x in range(field.lsbyte, field.msbyte+1)]
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empty_bits = accesswidth - current_bit + 1
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@ -113,28 +127,55 @@ class Register(Component):
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list_of_fields.append("{}'b0".format(empty_bits))
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# Create list of mux-inputs to later be picked up by carrying addrmap
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self.sw_read_assignment_var_name.append(
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self.sw_mux_assignment_var_name.append(
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(
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self.process_yaml(
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Register.templ_dict['sw_read_assignment_var_name'],
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{'path': x[0],
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Register.templ_dict['sw_data_assignment_var_name'],
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{'path': na_map[0],
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'accesswidth': accesswidth}
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),
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x[1], # Start addr
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self.process_yaml(
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Register.templ_dict['sw_rdy_assignment_var_name'],
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{'path': na_map[0]}
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),
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self.process_yaml(
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Register.templ_dict['sw_err_assignment_var_name'],
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{'path': na_map[0]}
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),
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na_map[1], # Start addr
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)
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)
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# Return an error if *no* read or *no* write can be succesful.
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# If some bits cannot be read/write but others are succesful, don't return
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# an error.
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bytes_read_format = ["b2r.byte_en[{}]".format(x) for x in list(map(str, bytes_read))]
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bytes_written_format = ["b2r.byte_en[{}]".format(x) for x in list(map(str, bytes_written))]
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sw_err_condition = self.process_yaml(
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Register.templ_dict['sw_err_condition'],
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{'rd_byte_list_ored':
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' || '.join(bytes_read_format) if bytes_read else "1'b0",
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'wr_byte_list_ored':
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' || '.join(bytes_written_format) if bytes_written else "1'b0"}
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)
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# Assign all values
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self.rtl_footer.append(
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self.process_yaml(
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Register.templ_dict['sw_read_assignment'],
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{'sw_read_assignment_var_name': self.sw_read_assignment_var_name[-1][0],
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Register.templ_dict['sw_data_assignment'],
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{'sw_data_assignment_var_name': self.sw_mux_assignment_var_name[-1][0],
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'sw_rdy_assignment_var_name': self.sw_mux_assignment_var_name[-1][1],
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'sw_err_assignment_var_name': self.sw_mux_assignment_var_name[-1][2],
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'genvars': self.genvars_str,
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'rdy_condition': "1'b1",
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'err_condition': sw_err_condition,
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'list_of_fields': ', '.join(reversed(list_of_fields))}
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)
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)
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def create_mux_string(self):
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for mux_tuple in self.sw_read_assignment_var_name:
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for mux_tuple in self.sw_mux_assignment_var_name:
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# Loop through lowest dimension and add stride of higher
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# dimension once everything is processed
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if self.total_array_dimensions:
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@ -270,7 +311,7 @@ class Register(Component):
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self.generate_active = glbl_settings['generate_active']
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# Empty array for mux-input signals
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self.sw_read_assignment_var_name = []
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self.sw_mux_assignment_var_name = []
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# Determine dimensions of register
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if obj.is_array:
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@ -119,7 +119,18 @@ read_mux:
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end
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default_mux_case:
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rtl: |-
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default: r2b.data = 0;
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default:
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begin
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// In case the address is not found, return an error
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r2b.data = 0;
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r2b.err = 1;
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r2b.rdy = b2r.r_vld || b2r.w_vld;
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end
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list_of_mux_cases:
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rtl: |-
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32'd{}: r2b.data = {};
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32'd{index}:
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begin
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r2b.data = {r2b_data};
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r2b.err = {r2b_err};
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r2b.rdy = {r2b_rdy};
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end
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@ -55,15 +55,40 @@ generate_for_end: |-
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end // of for loop with iterator {dimension}
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signal_declaration: |-
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{type:{signal_width}} {name:{name_width}}{unpacked_dim};
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sw_read_assignment_var_name:
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sw_data_assignment_var_name:
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rtl: |-
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{path}_rd_mux_in
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{path}_data_mux_in
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signals:
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- name: '{path}_rd_mux_in'
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- name: '{path}_data_mux_in'
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signal_type: 'logic [{accesswidth}:0]'
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sw_read_assignment:
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sw_err_assignment_var_name:
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rtl: |-
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{path}_err_mux_in
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signals:
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- name: '{path}_err_mux_in'
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signal_type: 'logic'
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sw_rdy_assignment_var_name:
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rtl: |-
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{path}_rdy_mux_in
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signals:
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- name: '{path}_rdy_mux_in'
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signal_type: 'logic'
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sw_err_condition:
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rtl: |-
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!((b2r.r_vld && ({rd_byte_list_ored})) || (b2r.w_vld && ({wr_byte_list_ored})))
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sw_data_assignment:
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rtl: |-
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/**************************************
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* Assign all fields to signal to Mux *
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**************************************/
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assign {sw_read_assignment_var_name}{genvars} = {{{list_of_fields}{genvars}}};
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// Assign all fields. Fields that are not readable are tied to 0.
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assign {sw_data_assignment_var_name}{genvars} = {{{list_of_fields}{genvars}}};
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// Internal registers are ready immediately
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assign {sw_rdy_assignment_var_name}{genvars} = {rdy_condition};
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// Return an error if *no* read and *no* write wa be succesful.
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// If some bits cannot be read/write but others are succesful, don't return
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// an error. Hence, as long as one action can be succesful, no error will be
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// returned.
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assign {sw_err_assignment_var_name}{genvars} = {err_condition};
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@ -0,0 +1,17 @@
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package srdl2sv_widget_pkg;
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typedef struct {
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logic [31:0] addr;
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logic [31:0] data;
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logic w_vld;
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logic r_vld;
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logic [ 3:0] byte_en;
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} b2r_t;
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typedef struct {
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logic [31:0] data;
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logic rdy;
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logic err;
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} r2b_t;
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endpackage
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